Changing Voltage on PS SPI when routed to EMIO

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Changing Voltage on PS SPI when routed to EMIO

Postby Kalicutt » Thu Jan 07, 2016 3:13 pm

Hello,
I am using SPI to talk to another board with the Zynq. In order to go to the right pins, I routed the SPI to the EMIO. I took care of the issue with multi master mode by tying SS_0 high, and made the bank voltage where the SPI were being routed to LVCMOS33. Despite all this, I am not seeing 3.3V logic when looking at the signals on an oscilloscope digital logic probe. The voltage is always 2.5V.
I read it was an issue with the PS-PL voltage level shifters not being enabled, however when adding the recommendations on page 47 of the TRM to the FSBL through the fsbl_hooks.c and making sure the operations and registers were correct, the problem persisted.
I am driving the SPI master using the Cadence SPI driver and sending simple signals. Any help on this matter is greatly appreciated. There was another post with a similar issue on the Xilinx forums, but they found the problem to be that their pins were being shorted, https://forums.xilinx.com/t5/Zynq-All-P ... 1086#M7355, which I am confident is not the case here.
Kalicutt
 
Posts: 24
Joined: Mon Nov 30, 2015 3:57 pm

Re: Changing Voltage on PS SPI when routed to EMIO

Postby Kalicutt » Fri Jan 08, 2016 2:04 pm

For anyone having a similar problem:

I found that the solution was that the voltage supply to the FPGA was insufficient as the voltage regulator for the GPIO pin banks default to 2.5 V at boot up. The voltage regulators on the Parallella must be reprogrammed in order to accommodate this. This is done through I2C coming off the Zynq chip.
Kalicutt
 
Posts: 24
Joined: Mon Nov 30, 2015 3:57 pm


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