Working with Vivado

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Working with Vivado

Postby theover » Wed Nov 18, 2015 6:58 pm

I've been working with the information in this thread:
viewtopic.php?f=51&t=3297

and now have an empty project that loads in the on the Parallella without problems, and at least gives a decently working and neatly fast enough interface from a C program to the Zynq FPGA (without the Epiphany code at the moment being merged in, for the sake of simplicity).

I have some other FPGA projects and ideas I'd want to couple with the AXi, but I want preferably to take a simple route to include them in Vivado, without creating problems, so I wonder what the best ways are to:

- Update a logic design (i.e. in the above example I replace the multiplier with something else)
- include Verilog with the VHDL project
- create connection between existing and new blocks, for instance add more pins to the "multiplier" code, and connect them with some GPIO pins

Now, I know I can do some of those things, and certainly I've hacked some things together that can work, but maybe someone can of the top of their head give s short summary to these questions!

T.V.
theover
 
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