Reloading elink

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Reloading elink

Postby frodo » Mon Oct 26, 2015 9:29 pm

Hi, I've successfully built the elink FPGA project in Vivado 15.3
I want to test this and will also want to test further FPGA development.
I won't want to keep rebooting to do this but will want to load the FPGA config from the Linux command prompt.
Are there any issues doing this?
I'm guessing I'd need to do something link

rmmod elink-module
cat image >/dev/xdevcfg
modprobe elink-module

Is there an e-link module? lsmod shows nothing so maybe the driver is built into the kernel.
If so what's the effect of loading a new image into the FPGA whilst Linux is running?

Thanks
frodo
 
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Re: Reloading elink

Postby frodo » Mon Oct 26, 2015 9:41 pm

As said in my original post there are no modules loaded into the Linux kernel.
Have found /dev/epiphany which I guess is the Epiphany device driver using eLink.
Is this device driver going to get messed up by loading /dev/xdevcfg whilst running?
frodo
 
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Re: Reloading elink

Postby frodo » Mon Oct 26, 2015 10:07 pm

Well, I just dived in and loaded my new bitstream to /dev/xdevcfg.
After this I ran the epiphany-sdk tests and they ran as before, i.e. matmul16 failed.

So maybe it's as simple as that. Alternatively, my FPGA reload had no effect :-)
frodo
 
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Re: Reloading elink

Postby kirill » Tue Oct 27, 2015 8:01 am

That's cool. I guess if there are no active AXI interactions during FPGA reload, AND your address assignments AND clocks do not change, drivers shouldn't notice anything. The safest way to ensure that no AXI interactions are happening is to unload modules that interact with AXI. You'll need to recompile kernel changing necessary drivers to be compiled as modules rather than baked into the kernel the way they are now.

Are you adding custom IP to design? Have you got it working under Linux?

I have managed to use this guide:
http://www.fpgadeveloper.com/2014/08/cr ... ivado.html

to create a test custom IP and integrate it into headless design by replacing one of the "AXI interface converters" with "AXI interconnect". I have tested that it works, but only in bare metal mode. Linux seems to be much fiddlier, probably have to modify device tree to expose custom IP to Linux.
kirill
 
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Re: Reloading elink

Postby frodo » Fri Oct 30, 2015 8:48 am

I bought the Parallella board for FPGA development rather than for the Epiphany chip. I wanted the Zynq 7020 rather than the 7010 (just greed :-]) and the Parallella board was not much more than a Zybo with the Zynq 7010. The Epiphany chip is a bonus and I'm only just discovering how big a bonus it is. I could disable the Epiphany chip and the eLink interface but I'd prefer to work alongside it.

I'm an experienced embedded systems developer with experience of ARM, co-processors, FPGAs, embedded Linux and hardware. Despite this I'm finding there's a lot to learn with the Zynq SoC. Thanks for the link.
I will be adding my own IP to the PL, quite disjoint from eLink. You're right I'll need to modify the device tree and provide a Linux device driver for it.
frodo
 
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Re: Reloading elink

Postby kirill » Sun Nov 15, 2015 7:48 am

I can confirm that reloading via /dev/xdevcfg works just fine.

I have documented the pocess here https://github.com/Kirill888/parallella-fpga-dummy-io/tree/master/sample

Bit stream I tested with doesn't include eLink, so I needed to terminate parallella-thremald service to avoid kernel crashes. I could load my bitstream, test it and then load back original with eLink, and tested that eLink is back with helloworld app.
kirill
 
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