How about some simple FPGA example "programs"

[theover]

Having installed and used Vivado 2014.3 to successfully (ignoring a number of warnings) create headless 7010 FPGA bit.bin files, and finally being able to in a fraction of a second loading a new FPGA design into the chip, and having verified a change in the FGPA indeed works as planned, I was thinking a bit about this new freedom to use FPGA programming files.

For audio purposes, it is handy to be able to very quickly change one FPGA setup for another, for instance containing different sound generators but I would like to cover the basis a bit. So: when changing the FPGAs programming "on the fly" (like from a script under User Interface control) of course we need to know at which point in time buffers are empty, IO pins have returned to some predefined state, and maybe some preparations for the logic circuit to change have to be taken (for instance lowering the volume or smoothly setting to zero DACs for audio purposes).

At this point, this is a Parallella idea, not primarily including the Epiphany, because that adds t the complexity, takes some AXI resources maybe available to example projects, and there's always the option to change the FPGA back to the original situation (I suppose currently the 2015.1 design) by pushing the normal bit.bin file through the programming device. So I presume I make sure all Epiphany activity is done, maybe run the "low power" program from the supplied sources, and with the to be loaded in FPGA bit file simply ignore the Epiphany inputs and set the outputs to zero or floating (3 state) conditions.

My questions to maybe some of you savvy people about the things Epiphany are: is that ok for the Epiphany chip, to ignore data, set the clock disable bit (or give it no clock at all)?

Also, suppose the Epiphany has been disconnected for the time being from the FPGA's activities, what's the way to send data down the AXI interface, I recall there was a mmap() call to do that as superuser in the beginning, but now that there's a normal Linux user based interface: how does that work, is there some page on that ? It's a shame if all that works get's not used, I guess, and Xilinx documentations doesn't talk about the Linaro Linux programming.

Anyhow, I think it can be good fun to make simple (fast FPGA compile time) projects like audio generator, frequency counter, led control, etc that can be loaded into the Parallella with an easy to use script for testing out logic circuits, but there needs to be communication with the Zinq's ARM cores!

I make it sound simple, because I've not got the time or the acquired skills to play around with the whole Zinq design in a short time, but I do have serious applications in mind, where the basis computations on the FPGA are a sequence of measurement, synthesis and correction of high frequency audio signal paths in practical use that cannot be easily achieved with other means. Short turnaround times of the Vivado compile are handy, and the idea of relative simple repetition of various primitives instead of painstakingly made complete hardware designs that are actually only needed for certain phases of computations that aren't normally combined.

Theo V.

[kirill]

I'm working on exactly that. So far I managed to create an emptyish design with only few bits from e-link library present. See attachment for screenshot. I had to remove TX/RX ports and also removed them from constraints file, it's probably safe so long as you don't create your own ports and accidentally attach them to TX/RX pins connected to Epiphany and use wrong voltage or direction.

My design worked, I tested it with bare metal app, but Linux didn't want to boot with that bitstream, after changing bitstream back to official, things worked ok as before, so I didn't fry anything. But then I also didn't leave it running for a long time either, so who knows.

It will take me some time to turn that into a step-by-step guide, but I plan on doing just that.

[peteasa]

looks like you disabled USB0 and USB1.. as these are wired in on the PCB I would have left them enabled... they might be configured in the bootloader. I would double check the processing_system customization for things that might have affected linux boot in some way and in general if its on the schematic so you cant use the pins anyway I would check how to disable it correctly or leave it in. I dont think that the lack of epiphany will cause the epiphany driver any problems and anyway you would see the problems in the boot log with a hint to the problem area. It there is no boot log from the serial port then its got to be something very early on like clocks or quad spi flash or something that the bootloader wants but cant find causing it to crash... just a guess.
Peter.

[kirill]

I had more time to look into it. First, I haven't changed USB settings, the only thing I changed on processing_system is disabling of AXI slave interface. I have now added "console=ttyPS0,115200n8" to kernel boot args and was able to see that it boots just fine and gets pretty far into the boot process, but then something gets triggered in user space and no more progress is made. I then added "init=/bin/dash" and was able to get to shell. My guess that it's some parallella specific service, maybe thermal watchdog that triggers hanging when eLink is not present in the bitstream.

[kirill]

I now have "example program" here:



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