IOSTANDARD conflict

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

IOSTANDARD conflict

Postby a_k » Wed Oct 21, 2015 2:12 pm

Hi,

I tried to implement my design, but it gives me the following error:

"[DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs:
RX_rd_wait_n (LVCMOS18, requiring VCCO=1.800) and DSP_RESET_N[0] (LVCMOS25, requiring VCCO=2.500)"

I have tried different IOSTANDARD's, but those are all Epiphany pins and I didn't change any of those. I only added constraints for the I2C pins and the GPIO pins I'm using for my part of the design, but those are on another IO bank. My constraints file:

Code: Select all
###############################################################
##  Location constraints for the Parallella-I board
##  3/12/14 F. Huettig
##  Updated to XDC format 7/1/14 F. Huettig
####
## This file defines pin locations & standards for the Parallella-I
##   and Zynq 7010 or 7020.  See the file parallella_z7020_loc.ucf
##    for pins added with the 7020.
## Timing constraints are defined elsewhere.
###############################################################

#  NOTE:  IOSTANDARDS for e-link and gpio have been removed
#    from these files.  IOSTANDARDS are to be set in the
#    verilog instead.

#######################
# Configuration Pins
#######################
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

#####################
# I2C
#####################
set_property PACKAGE_PIN N18 [get_ports {i2c_scl0}]
set_property PACKAGE_PIN N17 [get_ports {i2c_sda0}]
set_property PACKAGE_PIN T11 [get_ports {i2c_sda1}]
set_property PACKAGE_PIN T10 [get_ports {i2c_scl1}]

set_property IOSTANDARD LVCMOS33 [get_ports {i2c_scl0}]
set_property IOSTANDARD LVCMOS33 [get_ports {i2c_sda0}]
set_property IOSTANDARD LVCMOS33 [get_ports {i2c_sda1}]
set_property IOSTANDARD LVCMOS33 [get_ports {i2c_scl1}]

#####################
# Epiphany Interface
#####################
set_property PACKAGE_PIN H16 [get_ports CCLK_P]
set_property PACKAGE_PIN H17 [get_ports CCLK_N]
set_property PACKAGE_PIN G14 [get_ports DSP_RESET_N]
set_property IOSTANDARD LVCMOS25 [get_ports DSP_RESET_N]
set_property DRIVE 4 [get_ports DSP_RESET_N]
set_property PACKAGE_PIN F16 [get_ports TX_lclk_p]
set_property PACKAGE_PIN F17 [get_ports TX_lclk_n]
set_property PACKAGE_PIN B19 [get_ports {TX_data_p[0]}]
set_property PACKAGE_PIN A20 [get_ports {TX_data_n[0]}]
set_property PACKAGE_PIN C20 [get_ports {TX_data_p[1]}]
set_property PACKAGE_PIN B20 [get_ports {TX_data_n[1]}]
set_property PACKAGE_PIN D19 [get_ports {TX_data_p[2]}]
set_property PACKAGE_PIN D20 [get_ports {TX_data_n[2]}]
set_property PACKAGE_PIN E18 [get_ports {TX_data_p[3]}]
set_property PACKAGE_PIN E19 [get_ports {TX_data_n[3]}]
set_property PACKAGE_PIN E17 [get_ports {TX_data_p[4]}]
set_property PACKAGE_PIN D18 [get_ports {TX_data_n[4]}]
set_property PACKAGE_PIN F19 [get_ports {TX_data_p[5]}]
set_property PACKAGE_PIN F20 [get_ports {TX_data_n[5]}]
set_property PACKAGE_PIN G17 [get_ports {TX_data_p[6]}]
set_property PACKAGE_PIN G18 [get_ports {TX_data_n[6]}]
set_property PACKAGE_PIN G19 [get_ports {TX_data_p[7]}]
set_property PACKAGE_PIN G20 [get_ports {TX_data_n[7]}]
set_property PACKAGE_PIN H15 [get_ports TX_frame_p]
set_property PACKAGE_PIN G15 [get_ports TX_frame_n]
set_property PACKAGE_PIN J15 [get_ports TX_rd_wait_p]
set_property IOSTANDARD LVCMOS25 [get_ports TX_rd_wait_p]
set_property PACKAGE_PIN J18 [get_ports TX_wr_wait_p]
set_property PACKAGE_PIN H18 [get_ports TX_wr_wait_n]
set_property PACKAGE_PIN K17 [get_ports RX_lclk_p]
set_property PACKAGE_PIN K18 [get_ports RX_lclk_n]
set_property PACKAGE_PIN K19 [get_ports {RX_data_p[0]}]
set_property PACKAGE_PIN J19 [get_ports {RX_data_n[0]}]
set_property PACKAGE_PIN L14 [get_ports {RX_data_p[1]}]
set_property PACKAGE_PIN L15 [get_ports {RX_data_n[1]}]
set_property PACKAGE_PIN L16 [get_ports {RX_data_p[2]}]
set_property PACKAGE_PIN L17 [get_ports {RX_data_n[2]}]
set_property PACKAGE_PIN M14 [get_ports {RX_data_p[3]}]
set_property PACKAGE_PIN M15 [get_ports {RX_data_n[3]}]
set_property PACKAGE_PIN L19 [get_ports {RX_data_p[4]}]
set_property PACKAGE_PIN L20 [get_ports {RX_data_n[4]}]
set_property PACKAGE_PIN M19 [get_ports {RX_data_p[5]}]
set_property PACKAGE_PIN M20 [get_ports {RX_data_n[5]}]
set_property PACKAGE_PIN M17 [get_ports {RX_data_p[6]}]
set_property PACKAGE_PIN M18 [get_ports {RX_data_n[6]}]
set_property PACKAGE_PIN N15 [get_ports {RX_data_p[7]}]
set_property PACKAGE_PIN N16 [get_ports {RX_data_n[7]}]
set_property PACKAGE_PIN J20 [get_ports RX_frame_p]
set_property PACKAGE_PIN H20 [get_ports RX_frame_n]
set_property PACKAGE_PIN K14 [get_ports RX_rd_wait_p]
set_property PACKAGE_PIN J14 [get_ports RX_rd_wait_n]
set_property PACKAGE_PIN K16 [get_ports RX_wr_wait_p]
set_property PACKAGE_PIN J16 [get_ports RX_wr_wait_n]

#######################
# GPIO
#  First 12 pairs are present on all parts, next 12 on 7020 only
#######################
set_property PACKAGE_PIN T16 [get_ports {data1[0]}]
set_property PACKAGE_PIN U17 [get_ports {data0[0]}]
set_property PACKAGE_PIN V16 [get_ports {data1[1]}]
set_property PACKAGE_PIN W16 [get_ports {data0[1]}]
set_property PACKAGE_PIN P15 [get_ports {data1[2]}]
set_property PACKAGE_PIN P16 [get_ports {data0[2]}]
set_property PACKAGE_PIN W11 [get_ports {data1[3]}]
set_property PACKAGE_PIN Y11 [get_ports {data0[3]}]
set_property PACKAGE_PIN P14 [get_ports {data1[4]}]
set_property PACKAGE_PIN R14 [get_ports {data0[4]}]
set_property PACKAGE_PIN T14 [get_ports {data1[5]}]
set_property PACKAGE_PIN T15 [get_ports {data0[5]}]
set_property PACKAGE_PIN U13 [get_ports {data1[6]}]
set_property PACKAGE_PIN V13 [get_ports {data0[6]}]
set_property PACKAGE_PIN W14 [get_ports {data1[7]}]
set_property PACKAGE_PIN Y14 [get_ports {data0[7]}]
set_property PACKAGE_PIN U14 [get_ports {pclk1}]
set_property PACKAGE_PIN U15 [get_ports {pclk0}]
set_property PACKAGE_PIN V12 [get_ports {vsync1}]
set_property PACKAGE_PIN W13 [get_ports {vsync0}]
set_property PACKAGE_PIN T12 [get_ports {hsync1}]
set_property PACKAGE_PIN U12 [get_ports {hsync0}]

set_property IOSTANDARD LVCMOS33 [get_ports {data1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data1[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data1[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data1[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data1[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data0[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data1[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data0[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data1[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data0[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data1[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data0[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pclk1}]
set_property IOSTANDARD LVCMOS33 [get_ports {pclk0}]
set_property IOSTANDARD LVCMOS33 [get_ports {vsync1}]
set_property IOSTANDARD LVCMOS33 [get_ports {vsync0}]
set_property IOSTANDARD LVCMOS33 [get_ports {hsync1}]
set_property IOSTANDARD LVCMOS33 [get_ports {hsync0}]


Any suggestions?
a_k
 
Posts: 6
Joined: Fri Oct 09, 2015 12:31 pm

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