FPGA questions

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

FPGA questions

Postby Riwa » Sun Oct 04, 2015 12:39 pm

I'm trying to start with FPGA programming, I took the vivado elink project, add my own design block, add axi interconnect in order to use Master GP0 , that's mean I change the original design little bit, successfully generate the bitstream, then I want to know if I should use the dummy.elf provided in here github.com/parallella/parallella-hw/blob/master/fpga/old/projects/parallella_7020_headless/dummy.elf

Or export to SDK and generate new fsbl.elf
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Re: FPGA questions

Postby kirill » Sat Oct 17, 2015 4:37 am

My understanding is that fsbl runs from qspi, not from sd-card, so changing that is problematic unless you have breakout board and a JTAG programmer, as you'll need JTAG if anything goes wrong. The purpose of dummy.elf is just to overcome some limitations of Xilinx tooling: in order to generate parallella.bit.bin (binary version of the fpga bitstream) we need to use bootgen utility from Xilinx, in order to use that we need to provide an elf executable to package into boot.bin. But we don't actually use boot.bin instead we copy a bitstream only file to sd-card (-split option). This file is then loaded by u-boot, or maybe FSBL, not sure, but you don't need to change either of them, just update parallella.bit.bin file.
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