Parallella Community

Looks like you did a very similar thing to me. version.v is in elink-gold so is part of the design verification environment. I did a quick grep and only found TARGET_7Z020 in legacy hdl code. My guess is what you have is good to go. In my version of this I added the hdmi library parts from Analog Devices - and proved it with a build of linux with the appropriate drivers etc - see https://github.com/peteasa/parallella and in particular for the fpga part https://github.com/peteasa/parallella-fpga.

Oh for the next version... I mean https://github.com/parallella/oh.. looks like it is still 7020 based but as you have found it should not be too hard to convert.

Thanks for feedback peteasa. I swear I looked at your project on github just recently and haven't seen 7010 support, and now it's there. Good job! I'll try it out on my board. Having HDMI controller in PL can enable some nifty effects if connected to some custom logic. I'm not at the level to try something like that though, in fact I want to go the other way and have a completely bare project with just minimal needed to keep Epiphany chip in safe state. This would be a good base project for "first steps with FPGA" for people who are new to this, like myself.

This is very useful info. Thanks Peter. I guess I also need to keep DSP_RESET_N low and CCLK_N/CCLK_P constant with one being inverse of the other?

With regard to clocks, good idea to keep them the same as official release, but if really needed they could be changed past fsbl, either in a standalone app, or in the kernel driver space? Or does this need to be fixed prior to loading bit stream? Either way it's a lot more trouble, but still easier than getting break out board and JTAG to replace FSBL/u-boot.

We'll see how far I'll get with that.

I just installed Vivado 2014.3.1just for the occasion, so that I have the build environment of the recipe from this page:

https://www.parallella.org/2015/03/23/n ... in-vivado/

I got the zip file as described, opened in in Vivado, changed the target into the Zynq 7010 (which I have), did Tools-->Report-->reportipstatus "update All", opened the block diagram for e_link_top_i (double click in the "sources" window, double clicked on the parallella_gpio_emio_0 block, changed the number of GPIO's to 12 [11..0], clicked the GPIO_P and _N pins to reflect the same change, edited

./parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.ipdefs/src/gpio/hdl/parallella_gpio_emio.v

and changed NUM_GPIO_PAIRS to 12, then refreshed the hierarchy and pressed Synthesize, Implement and Generate bitstream. There was an error about a block ram initialization compatibility problem, and the mentioned timing problems, but all runs to success (took about 2 minutes, on non-SSD drive).

Got the fake .elf file (from the git location mentioned at the bottom of the above page in a comment), created the bit2bin.bif file, and then was stuck, because the command "bootgen" simply isn't available in the this Vivado distribution. Luckily I found one in Vivado 2013.4, so I used that one to create the bit.bin file. I put the file (name changed properly to parallella.bit.bin) in the /boot of the SD card with the latest Linux, booted up and: it worked. I only tested e-bandwith and e-led, and some user ports, but everything functions. In fact , the resulting .bit file compares (using "cmp") as the same as the supplied .bit file, except it is 4 bytes smaller.

T.V.

Thanks for the update. I think bootgen is part of SDK, so you need to install that as well as Vivado, or use one from other version, like you did.

You might want to read a comment by Jeff (Oct-5) on that same page, I think he provides a solution to the BRAM error, some extra parameter you need to add to one of the components.