Vivado project for 7010 headless

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Vivado project for 7010 headless

Postby kirill » Tue Sep 29, 2015 11:50 am

I have made a Vivado project for 7010 headless configuration based off the 7020 Vivado project release by Adapteva

I have a "desktop" version of the board, that I got specifically for "learning about FPGA stuff" (I know, not the best starter board for that, but there are other reasons). I was a bit dissapointed when I found out that only 7020 Vivado project was released. But after some poking around I managed to convert to 7010 and build what looks like a working bitstream. I have tested bitstream on my board and it seems to work. I ran some Epiphany sample apps, and they work ok. I done no further tests than that.

I have documented the process with README and shell scripts here

https://github.com/Kirill888/parallella-7010-vivado

Quick run down:

  • Convert project to tcl (http://www.fpgadeveloper.com/2014/08/version-control-for-vivado-projects.html)
  • Verify generated project still works for 7020 (by works I mean "can generate bitstream")
  • Update tcl code to setup 7010 based system instead
  • Update block design to remove GPIO pins that are 7020 specific (by editing tcl version of block design)
  • Remove 7020 specific GPIO constraints file from the project
  • Update version.v to specify 7010 as desired target

I also removed "update logs" from the project before converting it to tcl. I don't think they matter, and some of them were missing from the distribution anyway. Also I skipped "test_bench" block design. I'm very new to the FPGA/Vivado world, I would appreciate feedback from more knowledgeable members of the community, maybe I have missed something important.

I hope that the next release of eLink will include project setup for 7010 based boards as well.
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Re: Vivado project for 7010 headless

Postby peteasa » Tue Sep 29, 2015 6:00 pm

Looks like you did a very similar thing to me. version.v is in elink-gold so is part of the design verification environment. I did a quick grep and only found TARGET_7Z020 in legacy hdl code. My guess is what you have is good to go. In my version of this I added the hdmi library parts from Analog Devices - and proved it with a build of linux with the appropriate drivers etc - see https://github.com/peteasa/parallella and in particular for the fpga part https://github.com/peteasa/parallella-fpga.

Oh for the next version... I mean https://github.com/parallella/oh.. looks like it is still 7020 based but as you have found it should not be too hard to convert.
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Re: Vivado project for 7010 headless

Postby kirill » Wed Sep 30, 2015 12:34 am

Thanks for feedback peteasa. I swear I looked at your project on github just recently and haven't seen 7010 support, and now it's there. Good job! I'll try it out on my board. Having HDMI controller in PL can enable some nifty effects if connected to some custom logic. I'm not at the level to try something like that though, in fact I want to go the other way and have a completely bare project with just minimal needed to keep Epiphany chip in safe state. This would be a good base project for "first steps with FPGA" for people who are new to this, like myself.
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Re: Vivado project for 7010 headless

Postby peteasa » Wed Sep 30, 2015 7:28 pm

What I found was the Zynq clocks are setup with the fsbl so you have to have the same clock configuration (FCLK_CLK0 etc) see the configurable items in elink2_top.bd
Code: Select all
<spirit:instanceName>processing_system7_0</spirit:instanceName>....

Also you will need to keep the I2C interface ie stuff starting at
Code: Select all
<spirit:instanceName>parallella_i2c_0</spirit:instanceName>

and associated connections because the I2C interface is used to configure the supply voltages (GPIO is at 2.5V during boot and 2.9V later see ... http://parallellagram.org/parallella-fp ... sion-cards "In particular, unconfigured, the PMIC sets the FPGA GPIO bank to 2.5V during u-boot, and 2.9V thereafter. While you can use the I2C PMIC to change this to 3V3, there are consequences in terms of HDMI power consumption - and you still need to ensure you will not drive pins above 2.5V during boot anyway.")
Then there are the USB, UART configuration and the Ethernet configuration in the processing_system7_0 section.... You are still not free to use all the pins on the FPGA because the elink connection is dedicated to uses some...

There is an old thread about an FPGA sandbox at viewtopic.php?f=51&t=1772. Might be worth making a sandbox minimum configuration and posting in that thread when its done!

Good luck!

Peter.
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Re: Vivado project for 7010 headless

Postby kirill » Thu Oct 01, 2015 10:22 am

This is very useful info. Thanks Peter. I guess I also need to keep DSP_RESET_N low and CCLK_N/CCLK_P constant with one being inverse of the other?

With regard to clocks, good idea to keep them the same as official release, but if really needed they could be changed past fsbl, either in a standalone app, or in the kernel driver space? Or does this need to be fixed prior to loading bit stream? Either way it's a lot more trouble, but still easier than getting break out board and JTAG to replace FSBL/u-boot.

We'll see how far I'll get with that.
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Re: Vivado project for 7010 headless

Postby theover » Wed Oct 21, 2015 11:42 pm

I just installed Vivado 2014.3.1just for the occasion, so that I have the build environment of the recipe from this page:

https://www.parallella.org/2015/03/23/n ... in-vivado/

I got the zip file as described, opened in in Vivado, changed the target into the Zynq 7010 (which I have), did Tools-->Report-->reportipstatus "update All", opened the block diagram for e_link_top_i (double click in the "sources" window, double clicked on the parallella_gpio_emio_0 block, changed the number of GPIO's to 12 [11..0], clicked the GPIO_P and _N pins to reflect the same change, edited

./parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.ipdefs/src/gpio/hdl/parallella_gpio_emio.v

and changed NUM_GPIO_PAIRS to 12, then refreshed the hierarchy and pressed Synthesize, Implement and Generate bitstream. There was an error about a block ram initialization compatibility problem, and the mentioned timing problems, but all runs to success (took about 2 minutes, on non-SSD drive).

Got the fake .elf file (from the git location mentioned at the bottom of the above page in a comment), created the bit2bin.bif file, and then was stuck, because the command "bootgen" simply isn't available in the this Vivado distribution. Luckily I found one in Vivado 2013.4, so I used that one to create the bit.bin file. I put the file (name changed properly to parallella.bit.bin) in the /boot of the SD card with the latest Linux, booted up and: it worked. I only tested e-bandwith and e-led, and some user ports, but everything functions. In fact , the resulting .bit file compares (using "cmp") as the same as the supplied .bit file, except it is 4 bytes smaller.

T.V.
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Re: Vivado project for 7010 headless

Postby kirill » Thu Oct 22, 2015 10:34 am

Thanks for the update. I think bootgen is part of SDK, so you need to install that as well as Vivado, or use one from other version, like you did.

You might want to read a comment by Jeff (Oct-5) on that same page, I think he provides a solution to the BRAM error, some extra parameter you need to add to one of the components.
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