Building "parallella.bit.bin" from FPGA sources

[ArunD]

Hello...

Are the Github master sources for Parallella HW/FPGA dev ones that I should be using to build the "parallella.bit.bin" ? Or instead of master (presumably active development & possibly not stable/tested) should I be using one of the tagged branches? There are two active branches besides the master.

I tried using the master sources but am unable to determine which directory Xilinx project file I should be pointing Xilinx Webpack/Vivado to. only under fpga/old/hdl/elink-gold there is "elink_gold_ip.xpr" which seems to open without errors. Which is the correct project to use?

My Parallella board, the Desktop version, is new (less than a month old). It is setup for headless use. My intent in building the "parallella.bit.bin" at this time is to only change the GPIO signals to be LVCMOS_25.


I am still exploring the Parallella environment, and need more help at this time.

[ArunD]

Besides the master branch I also tried using . This too opens "fpga/old/hdl/elink-gold/elink_gold_ip.xpr" without errors. But if without any changes the synthesis phase reports 104 warnings, and the bistream generation phase reports 104 errors. And the default target it is "xc7z020clg400-1", and changing it to "xc7z010clg400-1" makes no difference.

What are the correct FPGA/parallella-hw sources to use to build the bitstream? What is the correct target part to use?

[ArunD]

Hello... knock-knock!

Surely there must be a repeatable process for building the software/FPGA artifacts to obtain constant results every time. As part of this a source code control system, the label/branch/tag for the sources in the source repository to use, and the procedure to build it. Could any one help point out where to get this info please? Is this obviously known and did I miss it?

As I had mentioned in my previous post, the board that I have is a Desktop Parallella. I am using the Xilinx Vivado (v2015.1) for synthesis and building the bitstream etc. Is there a specific version of the Webpack that is required?

[tnt]

There is https://www.parallella.org/2015/03/23/n ... in-vivado/

But so far I didn't manage to build a working bitstream out of it ...

[tnt]

Actually, my bad ... it works.

But you need to make sure your SD card uses the new Ubuntu 14.04 headless stuff because the old linaro stuff (even the old headless linaro) doesn't work. It boots but crashes when you access the elink.

[ArunD]

Hello,

Thank you for the response, this helps! I was becoming unsure what to do next for lack of a response.

The article you pointed to mentions of building the FPGA for the 7020. I have a Desktop/7010, would this work for it? The question was also posed in , but there wasn't a response.

[tnt]

Well you'll need to change the target FPGA to a 7010 but other than that it should work fine.

[ArunD]

[ArunD]

[ianguzv]

Hi ArunD and tnt, I'm trying to program the FPGA following these steps
https://www.parallella.org/2015/03/23/n ... in-vivado/,
But I'm stuck on step 6 because i don't have the dummy.elf file. I already generated the bitstream succesfully. It would be great if you could mail me the dummy.elf file or give me some suggestions and feedback.

Thank you guys !