Parallella Community

Hello...

Per I counted the FPGA cells that the eLink takes, and they add up to more than 37k which is more than the available cells in the Desktop Parallella. Per the Parallella manual the available cells are 28k for the Desktop.

How do I explain this to myself? Also, would it be true that I do not have any cells / resources left for implementing custom logic? If not how many cells are actually available?

Hi ArunD,

It looks like you totaled everything in the third column of that table to get your 37kCells, but that's not right because each 'level' of hierarchy shows the total # of cells for that level and all sublevels. For example, 'erx_fifo' shows 2711 cells, but that includes the rxrd_fifo (865), rxrr_fifo (857) and rxwr_fifo (989). The sublevels total 2711, meaning there are no cells used at the 'erx_fifo' level, only in the modules it contains. By adding everything together you are double- or triple-counting almost all the cells.

The number you should be looking at is the top-level total on the first line, elink=9809 includes everything, which is < 28k for the 7010 (but more than I remember, hmmm, seems like the fifos are using registers instead of memories...?). The elink consists of ecfg_cdc (994), eclocks (3), erx (5200) and etx (3596) for a total of 9793 cells in the submodules and 16 cells at the top level.

So you do have room for user logic, and a lot more room if you have the 7020.

-Fred