eLink FPGA project

[Riwa]

Hi
i'm a beginner. i've followed these steps https://www.parallella.org/2015/03/23/n ... in-vivado/

Run synthesis failed.

the errors are:

[Synth 8-439] module 'elink2_top' not found ["C:/Users/DELL/Desktop/eLink block project/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/bd/elink2_top/
hdl/elink2_top_wrapper.v":159]

[Synth 8-285] failed synthesizing module 'elink2_top_wrapper' ["C:/Users/DELL/Desktop/eLink block project/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/bd/elink2_top/
hdl/elink2_top_wrapper.v":12]

[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

where can I find 'elink2_top' module
thanks

[arush3]

Hi Riwa,

I'm also a beginner, but I hope these instructions help:

1.Click on IP Integrator.
2. Click on the IP Status tab. You will see many IP source files are out of date.
3. Click on the Upgrade Selected Button. Now you should be able to synthesize the project.

Best Regards,
arush3

[aimeehuang]

wow, i am also a beginer, and thanks arush.

[ianguzv]

I was having the same problem, but the instructions by Arush3 were very helpful, Thank you Guys !

[peteasa]

Using Vivado version 2014.3.1... how to I point the IP Integrator at the lastest source?

I have latest version of https://github.com/parallella/parallella-hw.git and have checked my software environment with the bitstream provided on branch 2015.1 using the hello_world application to test talking with the re-designed e-link. Now I want to build the fpga from scratch.

The description at https://www.parallella.org/2015/03/23/n ... in-vivado/ points me to a zip file, however this zip file has all the sources copied into the archive project so the sources are at $PPRDIR/parallella_7020_headless_gpiose_elink2.ipdefs/src that is part of the zip file and are all sources dated about April 16th. I need to update to the latest sources (about April 21st) that are stored in fpga/src/*

Not clear how to do that. As a result of using old sources my version of the fpga does not work.

I suspect that what is missing is an update to the zip file that references the latest IP blocks that are used in the 2015.1 bit.bin

Any ideas?

[tnt]

The sources that are in the archive are fine and they work OK ... you don't need the very latest.

If you build what's in the archive and it doesn't work, the problem is not the sources ...

[peteasa]

my question still stands as the release I am after is marked in Git as "Milestone: WRITE AND READ FROM HOST WORKS!"

Seems odd to be using a version where write and read from host may not work!

Peter.

[peteasa]

Hi tnt and others... an update...

I went back and re-created the fpga as suggested, ignoring warnings etc. It now works with the 2014.4 version of the sdk. Now I have hdmi working and plang to get hdmi sound running.

I have created a template project that included verilog for fpga build and kernel build etc (based on my yocto environment). If you want to help out with this the latest is on branch elink-redesign at https://github.com/peteasa/parallella.git that will pull all the bits together and create the bitstream and the linux sd card etc.. Looking at the oh project I could also wrap that into the yocto environment so that fpga and linux get built at the same time!!! Right now I will be happy if I can get the hdmi sound functioning.

let me know if you are interested.

[ycyang]

You can try " upgrade_bd_cells [get_bd_cells -hierarchical *] " in tcl console to update the IPs

[MiguelTasende]

I would like to make my mind clear on one thing...
I am, at the moment, not working (yet) with the Parallella FPGA. I am evaluating if that would be necessary/worth it for my project, so this is something that probably everyone in this subforum already knows...

This is what I am assuming from what I read, tested, etc.:

The current version in the 2015 Parallella headless image has an FPGA elink that goes a bit slow (I get about 45MB/s for sending data with e_write to a core in the Epiphany from Host [improves 2x if I use intermediate ERAM and double buffer, but adds complexity]).

There is a project which improved the elink here: https://github.com/parallella/oh/tree/master/elink

If I follow the instructions there and install that elink image, would I (theoretically) get 1GB/s of Tx/Rx transfer rate??
Is it just "something in queue" for the next release of the Parallella image, that has still not been added, but will surely be?
Has anyone tested it?
If that is not the situation: Is anyone working on improving the FPGA version of the elink? (I could join in a few weeks, when/if it turns to be the bottleneck of my software project...)

It would change a lot to know that the Parallella hardware is capable of achieving that transfer rate without "really hard"-hardware changes.

Thanks very much for your attention, and I am sorry to ask such "Parallella-FPGA noob questions"...