Epiphany FPGA communication.

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Epiphany FPGA communication.

Postby AndyC » Thu Sep 25, 2014 6:15 pm

Hi Guys,

What's the recommended way of going about this?

Cheers

Andy
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Re: Epiphany FPGA communication.

Postby FHuettig » Thu Sep 25, 2014 9:37 pm

Hi Andy,

Because the AXI-eLink interface logic is quite involved, and I don't expect that you want to give up control of the Epiphany from the Arm CPUs, I think the easiest way would be to use one of the unused AXI slave interfaces, either GP or HP, to route your read/write requests to the Epiphany interface. I expect that you can do this without taking any bandwidth away from non-Epiphany transactions inside the PS, the PS interconnect block should (I hope) be able to handle concurrent transactions between independent ports.

If you need the Epiphany to write to / read from your logic you'll have to use a master AXI port and assign it an address range that you then use on the Epiphany.

I do have it on my list to implement streaming interfaces to/from the FPGA fabric from/to the Epiphany, with either the Arm or Epiphany setting up a list of descriptors to determine how the data is distributed/gathered, but it will be a while before that happens.

-Fred
-- Fred -- Hardware Guy --
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Re: Epiphany FPGA communication.

Postby AndyC » Fri Sep 26, 2014 6:31 am

Hi Fred,

Thanks very much for the pointers.

Looks like I need a master AXI port, are there any restrictions on access to memory locations from the Epiphany or can it access anything?

Cheers

Andy
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Re: Epiphany FPGA communication.

Postby AndyC » Fri Sep 26, 2014 8:24 am

Hi Fred,

My hopeful first attempt at just writing to the 'correct' AXI address from the Epiphany caused the parallella to hang!

So I am obviously being a bit naive, how do you map an AXI address say 0x7AA00000 to the Epiphany?

Thanks for any help.

Andy
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Re: Epiphany FPGA communication.

Postby AndyC » Tue Sep 30, 2014 6:37 am

Anyone got any idea of how to do this?

I tried to map the AXI registers into the shared ram address range and XPS doesn't like this at all.

I'm stumped here.

Cheers

Andy
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Re: Epiphany FPGA communication.

Postby aolofsson » Tue Sep 30, 2014 9:10 am

You can't really move the memory space around, you'll need to live with the ranges defined in the zynq manual. For the Epiphany, this meant that we had to alias some of the addresses to enable bidirectional communication. Should also be in section 4.1 of parallella manual:
http://parallella.org/docs/parallella_manual.pdf

Example of ramapping code (line ~500)
https://github.com/parallella/parallell ... rallella.v

The Epiphany needs to write "East" so you will likely need to do something like what was done above.

Andreas
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Re: Epiphany FPGA communication.

Postby AndyC » Tue Sep 30, 2014 9:23 am

Thanks Andreas, I will take a look....
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Re: Epiphany FPGA communication.

Postby Melkhior » Mon Nov 24, 2014 2:13 pm

Did you succeed with the epiphany-fpga communications ?

I tried adding my own remapping to give access to my memory-mapped registers to the epiphany (this this thread for details), but it's not working.

I'm remapping (trying to remap...) 0x8F000000--0x8F000FFF (physical) to 0x60000000--0x60000FFF (the 4 KiB of memory mapping from the axi4lite core). Writes by the epiphany to those addresses no longer modify the shared memory (when I dump 0x3F000000, nothing changes, whereas I can see the epiphany stores just fine without my remapping). However, the data in the FPGA registers do not change. Nothing seems to break, but I've no idea where my writes are going :-)

new fpga constants:

Code: Select all
`define GCM_MAPPED_REG  20'h8f000
`define GCM_PHYSIC_REGH  4'h6
`define GCM_PHYSIC_REGL  4'h0


new remapping:

Code: Select all
   wire        gcm_mem_access;
(...)
   assign ext_mem_access = (elink_dstaddr_tmp[31:28] == `VIRT_EXT_MEM) &
                          ~(elink_dstaddr_tmp[31:20] == `AXI_COORD) &
                          ~(elink_dstaddr_tmp[31:12] == `GCM_MAPPED_REG);
   assign gcm_mem_access = (elink_dstaddr_tmp[31:12] == `GCM_MAPPED_REG);
   assign elink_dstaddr_inb[31:28] = (ext_mem_access ? `PHYS_EXT_MEM :
                                      (gcm_mem_access ? `GCM_PHYSIC_REGH : elink_dstaddr_tmp[31:28]));
   assign elink_dstaddr_inb[27:24] = (gcm_mem_access ? `GCM_PHYSIC_REGL : elink_dstaddr_tmp[27:24]);
   assign elink_dstaddr_inb[23:0] = elink_dstaddr_tmp[23:0];
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Re: Epiphany FPGA communication.

Postby AndyC » Mon Nov 24, 2014 2:55 pm

Hi,

No I had no success, I couldn't get it to work and gave up hoping that something may be available in the new version to make this easier.

I would be interested in hearing if you get it to work though.

Cheers

Andy
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Re: Epiphany FPGA communication.

Postby Melkhior » Mon Nov 24, 2014 3:37 pm

AndyC wrote:I would be interested in hearing if you get it to work though.


At the moment, that doesn't seem likely - I haven't the faintest clue of what to try next :-(
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