FPGA Partial Reconfiguration

[yanidubin]

This is a topic in and of itself, but started with Colin's comments on .

I just came across references to the project.

I haven't time to look into it now, but wanted to raise awareness that it exists.Based on their source code, they only support upto the Virtex5 series (last release was mid-2011). They are using the TORC library which is up to date with Zynq support - but not sure that helps any. I haven't seen anyone stating it actually works yet, but a Xilinx guy says on that once you have a partial bitstream, you can load it in the usual way (/dev/xdevcfg).

So we need to establish if this tool works with the Zynq, and if not what is missing - and whether the tool still works in general.

Given the Xilinx version being non-free, this is probably the best hope for partial reconfiguration for the hobbyist.

[yanidubin]

There is also an informative document from Xilinx , which is specific to the Zynq and shows how to prime the xdevcfg interface to receive a partial bitstream (page 13).

And the supporting to doing this using their tools. You can get a 30-day trial for this feature to try it out.

To make this generally feasible for the hobbyist, the aim would be to generate the static/partial bitstreams using a free open-source tool such as OpenPR to make this feasible.