Parallella Community

update: I thought this project was basically it but I wanted to give a shot to the Xilinx FIR_compiler IP, thus having the crossovers done in the PL instead of IIR filters implemented in the PS.

I'm pretty pleased with the results, it's not only conceptually better but the listening experience is also significantly improved.

Image #1
I made a simple IP (the FIR_compiler + a bram block to time-align each speaker) with 4 inputs:
- sys_clk = 100MHz Fabric clock
- spdif_clk = 128fs
- to_fir = signed 16-bit audio sample (lower 16 bits=left channel, higher 16 bits=right channel)
- reset = to ensure all the IP individual SPDIF counters start counting at the exact same time

and one output: the SPDIF EMIO

Then it's pretty straightforward to go bi/tri/quad... amps

Image #2
The measurements of my right channel:
- upper part = each amp separately
- light blue below (graphically dragged down a bit to be able to distinguish it) = all 4 amps

The FIR compiler coefficients are calculated from
(I made the slope pretty stiff for horn drivers)

attached are the VHDL source files.

Found this excellent article in Xilinx xcell about an upsampling method:


To easily experiment with it I wrote a simple Excel VBA utility to generate both the coefficients and output equations when given the number of taps and upsampling ratio (zip file below).

Image #1: current workflow
output
- from_SD: read from SD card in chunks of stereo 32K samples @44100 (PS)
- to_UPS: send to BRAM in 16 blocks of stereo 2K samples
- upsample to 88200 (PL)
- from_UPS: send to DDR in 16 blocks of stereo 4K samples @88200
- convolver: digital room correction convolution of stereo 64K samples (PS)
- to_SPDIF: send to BRAM in 8 blocks of stereo 8K samples
- split into 4 with FIR filters (PL)
- send to 4 SPDIF outputs (PL)

64K samples @88200 = 743ms

input
- from_SPDIF: read from SPDIF input (PL)
- send to DDR in 4 blocks of mono 16K samples @88200 (for measurement microphone)
- write to SD card (PS)

all transfers are using DMA and interrupts (double-buffers implemented when timing is critical)

Image #2: "Learning to Fly" with Zynq/Parallella
from left to right on the back panel:
- usb to power the system (and deploy/debug C# app with Visual Studio)
- 4 SPDIF outputs
- 1 SPDIF input (CD player or measurement microphone)

It's quite a feat to get all this to work good. I was almost fooled into believing the Upsampler Code promised a upsampling with a filter length of the order of a second with those big buffers being defined, which I would have jumped at to use and improve myself, but I found it's a matter of a pretty small windowed Sinc function, still nice, but I've got that easily. Someone should do a good work and make a convolver/upsampler able to use all the juice of those FPGA Memories and DSP Slices that can do a 64k size windowed weighing function, that would be superb!

T.

Since the digital amps support up to 192 kHz sampling rate and the external SPDIF oscillator is 22.5792 MHz, I went for 176400 upsampling.

- read from SD card in chunks of stereo 64K samples @44100 (PS)
- send to BRAM in 64 blocks of stereo 1K samples
- upsample to 176400 (PL)
- send to DDR in 64 blocks of stereo 4K samples @176400
- digital room correction convolution of stereo 256K samples (PS)
- send to BRAM in 32 blocks of stereo 8K samples
- split into 4 with FIR filters 1023 taps each (PL)
- send to 4 SPDIF outputs (PL)

below
loopback test where the SPDIF input is connected alternatively to each SPDIF output with a cable

added HiRez support: I purchased a 24-bit @88200 recording from Qobuz and made the necessary changes to accomodate this format.

There is now much more data to shuffle back and forth between PS/PL but the upsampling stage is skipped so I didn't expect any major problems.

Also, even though the 176400 sampling rate is working fine in my setup (it's getting tight but there is still ~15% extra bandwidth), it requires a bit too much of the FPGA Fabric resources and I have to use a Zynq 7020 instead, so for now I stick to the 7010 with 88200 sampling rate.

built a 2 x 50W digital amp with the ~10 bucks TAS-5112 from TI connected directly to 4 differential outputs on Parallella.

Not a high priority right now but I'll have to investigate why it's working pretty well only up to ~8/10KHz...

Standard CD versus High Resolution Audio (HRA) preliminary results

Originally I purchased the following recording:


The format is 24-bit @88200 sampling rate and I converted it down to 16-bit @44100 with CoolEdit to try a comparison of listening for track #5.

Standard CD format workflow
1- read a chunk of audio data
2- upsample to 88200
3- convert signed 16-bit to float
4- room correction convolution
5- convert float to signed 24-bit
6- crossover splits and output to 4 SPDIF

High-resolution workflow
1- read a chunk of audio data
2- convert signed 24-bit to float
3- room correction convolution
4- convert float to signed 24-bit
5- crossover splits and output to 4 SPDIF

bottom line: I believe this is as close as it can get for an apple-to-apple comparison so that we can focus on the audio resolution differences.

Since I know what is what, I also asked my wife for a blind listening test and I didn't tell her what to expect. We both agree that
although standard CD is pretty good, HRA has a more harmonious cohesion in space, greater details and better depth yet lighter
(we're both no audiophiles so probably about anyone would hear the differences with this audio setup).

pictures below: HRA files have a distinctive red frame

I always wanted to have only one audio clock across the whole digital chain. Many thanks to Christophe, the friend who pointed out that a kind of similar mod has already been done by others and for providing me the guidance to successfully hack my digital amps.

image #1 the playback diagram

image #2 feasibility: the 24.576 MHz original oscillator has been removed from one digital amp and the 22.5792 MHz from the audio playback module is injected instead

image #3 the back panel is getting pretty crowded!

I was kindly invited by Xilinx to make a presentation at the Club Vivado Users Group in Paris

Using the same unique clock across the complete system gives stunning results (in short: lower jitter = much better imaging), so I went for a bit of experimenting.

There are 7 clock connections needed:
- Parallella Zynq (22.5792 MHz)
- measurements microphone (22.5792 MHz)
- 4 x digital amps (22.5792 MHz)
- CD player (22.5792 / 4 * 3 = 16.9344 MHz)

Configurations tested:
1) clock buffer - 50 cm of 50 Ohms coaxial cable - RS-485 receiver
2) clock buffer - 50 cm of 50 Ohms coaxial cable - double Schmitt trigger inverter
3) lvds clock buffer - 50 cm of 100 Ohms shielded twin-coaxial cable - LVDS receiver
4) clock buffer - 10/100 BaseT pulse transformer - 50 cm of 100 Ohms shielded twin-coaxial cable - 10/100 BaseT pulse transformer - RS-485 receiver

All measurements made with a 2x400MHz 100MS/s oscilloscope.

picture #1
the measurement setup where each module is connected in turn to the digital amp clock input (an Altera FPGA)

picture #2
the measurements of each module where channel 1 is the reference clock and channel 2 the clock injected into the amp

picture #3
SPDIF eye pattern
the clock going normally to the amp is fed instead to the Parallella and the oscilloscope channel 2
is hooked to one SPDIF output while the trigger is from channel 1 which is the reference clock