Disable Elink in FPGA [solved]

[moses_rotesmeer]

Hi,
unfortunately my PL Design is slightly too large to fit the design even with different optimization settings (I might switch to the 7020 in long term to overcome this problem).
Since this design is only for a proof of concept where I actually don't need to use the Epiphany Chip, I'd like to remove the E-Link from the design.
So I've the following questions:
1) If i disable the Parallella Instantiation, is it still possible to program the FPGA from the PS (by writing the bitfile to the sdcard or using xdevcfg)
2) Do the Epiphany Pins have to be held at a particular level (H/L) in order to avoid damage of the chip or can the Elink design simply be removed temporarily
3) (nice to have) What would be a good way to minimize the Power Consumption of the Epiphany while it is not used (e.g. hold in reset?)

Cheers,
moses_rotesmeer

[FHuettig]

[moses_rotesmeer]

Thanks!