A few requests for the FPGA design

[bithead]

[theover]

There are few tutorials on the web since the advent of the Zedboard a few years ago, on how to connect logic to the ARM cores and get data across . Of course it's easier to first cut out an properly disable the peripherals connected to the FPGA part of the Zinq like the Epiphany and the HDMI head. If they need to remain connected, not only must their pins remain connected and part of the active UCF file, bit the added logic to the AXI connectors must leave the efficiency and the timing of the Epiphany and HDMI logic intact. I know from experience that that may well work, but simply adding logic and complexity can send the ISE logic compiler of to (slightly) other external behavior without that the designer notices, and then things can possibly not work right anymore. That's like a hard part of hardware design, and it's not always automatically ok, no matter how desirable that may be.

Any how, non-demanding little extra state machines should get verilog/vhdl compiled in good enough, which I too find an interesting thing to work on. It may be, that for certain experiments, it can be automated what logic is created by an external tool like my flow simulator, and also the communication with the additional FPGA logic can probably be automated, like on the bottom of this page:



My main interests would lie in the making of serious additional FPGA computations, utilizing DSP IPs and FPGA FFT IPs, and on the other end, I'm formally educated in Network Theory after all, it would be very cool to try to let the Epiphany act as new parallel LISP processor, aided by the FPGA, but only to actually compute faster than a PC can, for instance.

I'm afraid that would take quite a bit of work beyond most BSc EEs, and isn't very profitable at the moment...

T.

[over9000]