The top level module is chosen by the designer - it defaults to the top of the design tree, or you can right click on a sub-module and select "set as top module". You might need to change the default if you were testing a subcomponent, or had a large design that spanned multiple FPGAs
It is the inputs and outputs of this module that gets connected to the external pins of the FPGA (or to the internal connections to the ARM cores).