pin constraints

[rec]

[FHuettig]

Hi rec,

Please see the github repository . This has fpga projects for the board including all the constraints files, see the README for the directory structure and what's where. These projects use the Xilinx tools PlanAhead and XPS, though we'll be moving to Vivado at some point. You can get a free WebPack license for these tools from Xilinx.

As long as you start with the constraints and top-level IOs provided there is no risk of damage, but for example redefining inputs as outputs which then contend with outputs from other components risks damage to the FPGA, the external component, or maybe both. In general all these components are fairly tough but it's always better not to test them. A bit of care when making changes is worth the time.

-Fred

[rec]

Thanks Fred,

When I'm following a tutorial in ug873-zynq-ctt.pdf, Zynq-7000 All Programmable SOC: Concepts, Tools, and Techniques (CTT), I get to a point where I'm defining the system in XPS/EDK and I am offered the choice of three system templates: Zedboard, ZC702, and ZC706 Development Boards.

Could you make a template for the Parallella that would serve to define adequate constraints?

The contents of parallella-hw/fpga/edk appear to contain most of the processing system constraints, though I thought I saw some comments that implied that some constraints -- the IO conventions -- were being deferred to the Verilog for the Elink and GPIO connected pins.

Would that directory provide adequate constraints if I just copied it into a project?

The first thing that happened when I attempted to make my own project as a peer of your headless projects was that the shared fpga/edk processor definition got overwritten with modifications. That was confusing since I had opened my own project to specifically avoid modifying your projects, and then I find I've inadvertantly modified sources in a directory remote from my project.

Thanks,

-- rec --