Parallella Community

Just a n00b here, bumbling my way through an FPGA design to see if I can embarrass someone better prepared to take it over from me. I've gotten the ISE Webpack 14.7 installed and licensed. I've been ferreting out what I can find in the documentation. But still I'm puzzled about a few things:

1) Where is the source for the HDMI interface? I've seen the vague pointers to and hand waving at Analog Devices pages which cover multiple reference designs none of which are clearly identified as suitable for the ADV7513 or for the Parallella. There must be a source for the bitstream that you're delivering to us, no? Where is it? How much of the FPGA does it use? How much power is it consuming? How do we rebuild it with modifications?

2) How is the parallella.bit.bin file on the boot partition created? It is not the bitstream format produced by the Xilinx tools used to produce parallella-hw/fpga/bitstreams/*.bit, it's been processed into another format. What is the format? How is the processing done? Can another bitstream be substituted into its place by simply copying the processed bitstream file onto the boot partition? Or is there some more complicated process like parallella-hw/boards/parallella-I/firmware/README?

3) How is the FPGA configuration managed after system boot? There is code in the uboot source to DMA the bootstrap bitstream into the configuration RAM during boot. That's fine if you're running on bare hardware. The Xilinx documents claim that it is possible to read and to write the configuration RAM at any time. What are the tools for doing this? How do I install the bitstream parallella_e16_headless_nogpio_7020.bit to test if it works? Has anyone tested it?

I'm sure there will be more questions in time, but those are the ones that prevent me from recreating parallella-hw/fpga/bitstreams/parallella_e16_headless_nogpio_7020.bit from sources and testing my build process.

-- rec --

[edited to fix the ADV7513 part number]

Thanks Fred --

That should keep me busy for a few days.

-- rec --

Awesome! Thanks for the info, rec. I've been meaning to look into that process for weeks. -Fred

Apart from some corrections I think most of the mentioned answer components were already mentioned in the past.

My question is: do you get easily from the FPGA verilog to the bit file with the ISE tools, and a good working connections with the ARM CPU (like in other projects such as the Zedboard has been discussed quite a while ago), to begin with ?

T.