Headless Bitstream

Forum about Parallella boot process, linux kernel, distros, SD-cards, etc.

Headless Bitstream

Postby miro » Thu May 15, 2014 6:40 am

Hi Everyone,
I am trying to use my Parallella in headless mode. I created the SD Card as described, and this is booting fine, starting Linaro with XCFE on HDMI. Then I downloaded the parallella_e16_headless_gpiose_7020.bit.bin from github and replaced it on the SD-Card naming as described. But the Parallella won't boot up then.. HDMI is as expected off, but I don't get the network working. (unfortunately I don't have serial cable, so I can't see what went wrong. ) Renaming the original parallella.bit.bin with HDMI back boots up immediately...(with working network)

Does anyone got this working? If so, can someone post me the md5 of the bin file, if its downloaded correctly?

Thx
Miro
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Re: Headless Bitstream

Postby 9600 » Thu May 15, 2014 8:28 am

Hi Miro,

I get:

dad03fff40a9b31e807e0f9291657517 parallella_e16_headless_gpiose_7020.bit.bin

Note that the Linux device tree will also need updating if the Parallella is being configured without a HDMI controller. I'd also strongly recommend getting a serial cable so that you can see what is going on, but as has been pointed out elsewhere, you should be able to put the SD card in another machine to read the logs.

Cheers,

Andrew
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Re: Headless Bitstream

Postby miro » Thu May 15, 2014 12:04 pm

Thanks, my checksum differs, so I'll have to download it again.. And thanks for the hint, for sure this one can make troubles too.. I'll look for one suitable serial cable for me.. :)
meanwhile I'll keep it in HDMI and try to get roff the matmul-16 error :cry:
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Re: Headless Bitstream

Postby 9600 » Thu May 15, 2014 1:04 pm

miro wrote:Thanks, my checksum differs, so I'll have to download it again..


Just to check, you are cloning the parallella-hw repository using git or else selecting to download it as a ZIP file, and not right clicking the bitstream in GitHub and selecting to "Save as..." ? Apologies if you are fully familiar with the difference, but thought it worth checking.

Cheers,

Andrew
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Re: Headless Bitstream

Postby miro » Fri May 16, 2014 3:51 pm

Hi Andrew,
sure, that was a good question :-) I was dowloading the bitstream "as raw view". At least the content has similar structure to the original file (biary diff). I guess it was the device tree. I downoaded it from the tgz archive togheter withthe device tree and now it is working fine in headless mode (howver the md5 differ to yours, so its still different one) ;)
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Re: Headless Bitstream

Postby dpavlin » Sun May 25, 2014 3:13 pm

I'm trying to disable hdmi on my parallella board and I have few questions.

I'm using bitstream from github parallella-hw/fpga/bitstreams

Code: Select all
74faaeb898dd14b8d5b716e84726b9b0  parallella_e16_headless_gpiose_7020.bit.bin


I also modified device tree to remove hdmi configuration (and audio) but now my boot stops with:

Code: Select all
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0xc05e07c0 - 0xc05e07f4
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72360000, Cache size: 512 kB
CPU1: Booted secondary processor
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated.
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
regulator-dummy: no parameters
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
zynq_gpio e000a000.gpio: gpio at 0xe000a000 mapped to 0xf0010000
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
bio: create slab <bio-0> at 0



I noticed that next line in successful boot is

Code: Select all
vgaarb: loaded


so I might need to remove this module from kernel?

I can load headless fpga stream into running kernel, if this helps.

I suspect that I have to add gpio pins into device tree, but I'm not quite sure how to do that. Where can I find correspoding dts files? Only one I found so far is parallella-hw/boards/archive/gen0/projects/p16_z7020_hdmi_600mhz/boot/devicetree.dts
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Re: Headless Bitstream

Postby FHuettig » Mon May 26, 2014 5:40 am

Hi dpavlin,

Sorry about the devicetree confusion, what you are reporting is exactly what happens when you use a devicetree that includes the HDMI components with an FPGA configuration that does not (stalls on vgaarb). Please see: viewtopic.php?f=10&t=1069&p=7965#p7965 for copies of both devicetrees.

dpavlin wrote:I suspect that I have to add gpio pins into device tree, but I'm not quite sure how to do that.


Both the devicetrees I posted include the GPIO driver, which gives access to all available GPIOs. There is only one GPIO available directly on the board, GPIO7 controls the LED on the Zynq, but there are 48 single-ended GPIOs starting at GPIO54 available on the GPIO connector using the configuration you have. The order of the signals may not be clear because the schematic assumes differential signaling, but the first GPIO is on pin 3 (after the two VDD_GPIO pins), next is on pin 4, then pin 5, etc.

I've written a demonstrator program for GPIO which I'll publish this week, in case it can be of any help.

-Fred
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