Peripherals and Interfaces of the SoC

[DEPC]

I have been looking at the datasheet of the Zynq SoC and just wondering without increasing complexity, if you are only planing on populating one of the Ethernet and USB ports each, is it possible to have the spare Ethernet and USB ports go to the expansion GPIO headers or if not could there be access to them via solder pads.

I know we don't wont to make this 1st Dev board complex just wondering what was the aim is with the Interfaces.

Thanks

[jeinstei]

That's a great question. I'm a bit curious myself. We work with Freescale Tower kits regularly, and they did a great job of providing a header that provides access to almost every pin, regardless of what other peripherals are hanging off it.

Just curious, but where is the Zynq SoC datasheet? Does Zynq provide an IDE, or do we need to use libraries and integrate them?

[fmotta]

I have requested I/O info a few times and still have none.

It'd be nice to determine what applications I can apply this toward based on what connectivity I will get...

It'd be a pain to have to use Linux mmap I/O as the only I/O for data... that'd be be quite a pain.

[DEPC]

The datasheet I found is this one http://www.xilinx.com/support/documenta ... erview.pdf

Coming to think off it I'm hoping that I got the right SoC.

[fmotta]

[DEPC]

Cool thanks, I have done very limited amount of VHDL coding for FPGA's but I'm just not to familiar with the hole physical CPU's surrounded by the gate array logic, if the Ports are limited to very specific pins or they can be routed to be more easily accessed.

EDIT: Found the MIO table in the ZYNQ technical reference manual and answering my own original question, seeing that ware using the ZYNQ7010 (probably the CLG225) it only supports one Ethernet and one USB.

[aolofsson]

Slight correction, it supports 1 ETH and 2 USBs. It's the zynq7010 in the 400 ball package.

[DEPC]

Awesome thanks. That cleared it up for me.

[Naveed123]

this is very very possible to have the spare Ethernet and USB ports go to the expansion GPIO headers or if not could there be access to them via solder pads.