Specification / Schematics

[Veqtor]

Still want to see a board layout with GPIO pin header placements so people can begin work on "shields"

[pbreed]

Question about board design rules....

What board design rules are you using? IE trace and space, via sizes and via types etc...

Any blind burried or filled via in pad?

What is the smallest device/ball spacing on the board?

How do yo think that impacts systems cost and have you identified a PCB vendor for both prototype and production?

I've yet to find a low cost prototype vendor that can do ball spacing under 1mm.

[mrgs]

[off] 'Guessing game picture', until we get the specification tonight(!) I have some tips. Have You got any? [/off]

[tnt]

I was hoping to have the spec when I woke up this tuesday morning, but no such luck

[trioflex]

[trioflex]

[tnt]

I would guess 4 is a CPLD

[trioflex]

[tnt]

heh, couldn't see the power pad on the picture above and I thought it was 100pin, not 64. And since the prototype had a MAX2 CPLD on them ... (not really sure why it was needed though)

[aolofsson]

Sorry to disappoint again. Almost there.
Andreas