Specification / Schematics

[tnt]

Hi,

The kickstarter update said more info about the board would be published by 15th Dec, when can we have more infos ? (and even schematics, even early/temporary ones).

Cheers,

Sylvain

[alexrp]

As someone who works on compilers and VMs, I'd especially like to see a more complete ISA reference. The one included with the SDK doesn't have any details on instruction encoding, for instance.

[ysapir]

[grahamh]

When the mechanical and electrical definitions for the board edge I/O connectors are stable, it would be helpful to have those, in advance of full schematics and board info. I would like to be able to work on interfacing some SDR hardware to the Parallela board while waiting for everything else to happen.
--- Graham

==

[fmotta]

[Veqtor]

So... where is it? It's been a month since the board spec should have been released...

[mrgs]

[tnt]

Where did you get "N_CORE * 2 * CLK_CPU" from ? AFAIK, it's dual issue, but can't issue two floating point ops at the same time, so it'd be 8..16 GFLOPS + 8..16 GIOPS at best.

The E16 will be in 65nm tech according to another thread. For the frequency, good question. One of the latter screenshot seems to display 600 MHz.

Also, the 99$ was the kickstarter amount, but in an interview I've read, it's mentioned as a "price to not loose too much money per board", so I wouldn't be surprised if the retail price once generally available is higher than this (which is also not usual for kickstarter projects to give an advantage to the pledgers vs the general buyers).

[mrgs]

@tnt : Hi, ... Well, You are right.
- The GFLOPS measure is not correct. We should use GOPS. "Giga Operations Per Second" or as You've written float + integer. (It fits for 'dual issue') To answer for Your questions: It appears at the Parallella page on Kickstarter site. Something like this : 90 GFLOPS(!) ~ 2 * 45 GHz ~ 2 * 64 * 700 MHz. --- Additionally this is regarding to E64 --- So, we 'can talk' about 16..32 GOPS. (Oops)
- E16 with 65nm: Well, I missed it. Thank You. 'Without any knowledge' about this tech, I just guessed: The 28 nm and 'little more money' give better (less power hungry, more CLK...) and cheaper chip.
- 99: Well, 99 is a very nice price for a Parallella board. I think up to 200 is also acceptable for everyone who is 'looking for' something like this.

I look forward for more fixes [and|or] details about the board. Plz.

Regards, Gabor

[mrgs]

Some additionally 'informal' data for 'GFLOPS' computing, based on the E_Arch_Ref paragraph 6.1.1 (about the eCore CPU): " ... This balance of performance and data throughput makes performance levels close to 2 GFLOPS attainable in a large number of signal-processing kernels." So, 2*#CPU [GFLOPS]. I think, these 'theoretical' (abs.max)?! computing numbers are quite nice numbers. BUT(!) Most significant measure is the G(FL)OPS/W for 'me'/everyone?! at the Ephiphany Arch. --- We can talk about [1..32]*GFLOPS at n*[W] range. Regards, Gabor.