Parallella Community

i'm certain this has been answered before but i can't find where. ::/

when directly accessing memory on another core, is there any sort of arbitration system to resolve one core trying to read and another trying to write write to the same memory on the same cycle or is it first come first served?

depending on the answer, i may have many follow up questions.

As per page 32/126 of the Epiphany Architecture Reference Manual ( section 6.3 Mesh-Node Arbitration ) : there's arbitration at the mesh node crossbar switch, for which a table of cases is provided.

Cheers, Mike.

First of all, all transactions are guaranteed to be carried out _eventually_.
As for multiple transactions, you have to look at it like this:

Every node has 4 neighbours, and is connected to those by a bi-directional bus.
Every direction of this bus consists of latched inputs, and links to the other core.
On a write, the bits to be written are latched into the appropriate bus (one of the four busses, routing rules are described in the architecture reference).
Those bits are then, should the next core not be busy, latched via the linking into the neighbouring core, on the next clock cycle.
Should, however, the other core be busy (that is, it is already receiving data from another core, which it prioritised via arbitration), no data is transferred in this clock cycle. The latched keep their state, no data is discarded.

Hence the network locks recursively. If, for example, we were to write more data to the same bus (which still has data latched), the write (or STR) would block, until the bus frees up.

(This might not entirely conform to the actual implementation, but should suffice for your purposes.
I would, however, like to know, whether each core can only accept one ingoing bus transfer per network cycle.
Another possibility would be, that every node can accept any number of transfers each cycle, provided they don't collide, that is, they don't share the next hop on their route)

Also: Can 4 write transactions, each from a different neighbouring core and targeting a different memory bank, complete in the same cycle?