Re: Concerning the IDLE instruction
Posted: Tue Sep 24, 2013 7:25 am
Ok, good to have the info.
But even then.
- Aren't the instruction fetched 8 bytes at a time ? so aligning could guarantee execution one after the other.
- Then even if both are executed at E1, the pipelining could still delay the interrupt (because if the interrupt is triggered right after GIE enabled it during E1, does it flush the pipeline and prevent the IDLE to execute in E1 or does it continue to execute what's already in the pipeline and just fetch the next instructions from the interrupt handler).
There are so many things I can think of that can make this race happen or not that the only way I can think of to be sure would be to simulate the HDL ...
But even then.
- Aren't the instruction fetched 8 bytes at a time ? so aligning could guarantee execution one after the other.
- Then even if both are executed at E1, the pipelining could still delay the interrupt (because if the interrupt is triggered right after GIE enabled it during E1, does it flush the pipeline and prevent the IDLE to execute in E1 or does it continue to execute what's already in the pipeline and just fetch the next instructions from the interrupt handler).
There are so many things I can think of that can make this race happen or not that the only way I can think of to be sure would be to simulate the HDL ...