Parallella Community

These are the documented Errata for the E16G3 (16-core) chip:

Errata 0 (Reset sensitivity, Functional):
To guarantee a correct and repeatable reset wakeup sequencing, the RXI_WE_CCLK_{P/N} signal must be held stable for the duration of the rising edge of RESET_N.

Errata 1 (DMA Throttle, Performance):
The DMA engine bandwidth per channel is stuck at 50% throttle, meaning that each DMA channel can transfer at most 1 double word every two clock cycles.

Errata 2 (NOC FIFO Full, Performance):
The FIFO interface between the compute node and the Network-On-Chip currently indicates FIFO full too early, causing a degradation in peak outgoing transfer bandwidth from the Epiphany processor node to the eMesh NOC.

Errata 3 (Software Exception, Functional):
On a software exception, the PC jumps to address 0x4 and halts instead of continuing with the exception service routine.

These are documented in the E16G3 REV 14.03.11 "preliminary datasheet (subject to change)". I haven't checked for more recent versions, and I haven't checked which of these Errata apply to the E64G4 (64-core) chip.

Please check if you are affected by Erratas 1 and/or 2.

Ok. I figured out what I was doing wrong.

If I have only one core that creates extra traffic then it does not matter to how many other cores he will send data because due to Errata 1 the DMA engine can only output 1 DMA double word every other clock cycle. Hence the NoC will have plenty of time.

In my program I introduce different cores in between so for example: sending from core 1 data to core B, from core 2 to core 7 and core 3 to core B. Then I get a expected decrease in the bandwidth.

Thanks again for the help!