Parallella RAM

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Parallella RAM

Postby jgalyardt » Wed May 25, 2016 6:39 pm

Does anyone know whether there are plans to increase the available RAM on the Parallella board to something like 2 GB per core? I realize that there are issues with this, including memory address space, bandwidth, etc., but it would make the board that much more useful for people who want to run memory hungry applications, e.g. hydrodynamic simulations.

Cheers,
Jason
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Re: Parallella RAM

Postby sebraa » Thu May 26, 2016 1:11 pm

In the current Epiphany, each core "owns" 1 MB of the address space, and all cores share the same 4 GB address space. This means that anything beyond 512 KB per-core RAM is simply impossible in the current system. The local memory is supposed to be scratchpad memory, with the bulk of the data stored off-chip.

Large amounts of SRAM are economically infeasible, so you are talking about DRAM then. This is much harder to incorporate into the same die as the cores and has different characteristics, so this is very unlikely. Simply said, 2 GB per-core memory is not going to happen.
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