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Parallella Community • View topic - the RAM

the RAM

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

the RAM

Postby 420maki » Tue Mar 05, 2013 5:53 am

i know that the 1 gb sdram is soldered in, but is there any way to get around this? I apologize in advance because i dont know too much about computers. could you solder more or ram in, or break off the old ram and replace it and resolder a new one in. (i ask mainly because i would like to have the option to play some games on it, if that is even possible)
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Re: the RAM

Postby 9600 » Tue Mar 05, 2013 9:06 am

Andrew Back
User avatar
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Re: the RAM

Postby trioflex » Tue Mar 05, 2013 1:51 pm

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Re: the RAM

Postby timpart » Tue Mar 05, 2013 5:28 pm

The DDR memory controller on the Zync chip which handles memory access for the system can only address a maximum of 1 GB (see page 243 of its TRM) so it would be very hard to get usable access to more than 1GB even if a bigger chip was put in.

Tim
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Re: the RAM

Postby 420maki » Tue Mar 05, 2013 6:00 pm

thank you very much everybody for all the info. certainly set me clear.
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Re: the RAM

Postby piotr5 » Tue Mar 05, 2013 8:44 pm

does anybody know more about this topic?

I could understand when more ram would require more watt and therefore some problems with overheating or somesuch could evolve (however this kind of problems are usually solved by a new generation of memory chips). but other than that I really expected a 32bit system to address 4gb by default. similar with an intel-chip used in many laptops: even though the processor is 64bit it can use only 2gb! does anyone know how this limitation could be worked around on the zync-chip? maybe some sort of memory-switching, additional ram on a daughter-card? is there anything that could technically be done with usual home-equippment? (i.e. chips definitely cannot be swapped!) anyone experience with enhancing such a limited memory?
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Re: the RAM

Postby wuher » Wed Mar 06, 2013 8:20 am

Theoretically you could write your own memory controller in programmable logic section of the ZYNQ but I'm not really sure if there is enough logic resources to implement it and pins to connect another memory Enhancing the "hard" memory controllers with programmable logic would be very hard in the best case and might even prove impossible.
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Re: the RAM

Postby Kcinnay » Sat Mar 09, 2013 1:46 pm

It should be possible to use SERDES or even IDDR and ODDR [1] I/O ressources with a DDR3 controller for FPGA without memory controllers like Virtex5 [2].

The controller would take ~2% [2] of the Zynq 7020 FPGA area assuming similar synthesis result for Virtex 5 and Zynq 7020.

With the 48 signals available on the PEC_FPGA, it could be possible to connect a 8b/16b wide DDR3 using the PL I/O of the Zynq -- if 1.2/1.5 I/O levels [3] are available on chosen banks (I'm not sure).

Anyway, the performance will be lower than with the hard memory controllers of the Zynq and the PEC connector might impact performances.

Using the 24 differential pairs as a link with another FPGA dedicated to a DDR3 chip/SO-DIMM could give better performance imho.

[1] :
[2] :
[3] :
Y.
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Re: the RAM

Postby theover » Sat Mar 09, 2013 3:11 pm

Dynamic ram isn't very fast concerning response time for random access patterns. So connecting another ram is of course possible provided there are sufficient pins left, but it isn\t easy (I've worked on it successfully in Open Source though), and especially, it isn't *that* fast, unless you know how to stride your access patterns and use a controller which can work with efficient page access and smart data streaming facilities of the latest generations of fast DRAMS.

Of course the FPGA has an amount of block- and random logic ram, which isn't in the gigabyte range though, but that is very fast ram. And it may well be feasible to connect some amount of static ram to the FPGAs external pins, provided there is still competitive static ram to be had. Also this is an easier and less delaying interface to create, but, like with all interface/controllers: it sounds easy, but testing the system so that it repeatedly over all kinds of versions and hardware component variations becomes reliable in the 1 error per lest say 100,000 hours op operation, may well be excruciatingly hard, when you don't know all the exact things going on. That's why hardware designers shouldn't be IT-ers, I'm sure. I have another (not expensive) FPGA board lying around, with a megabyte of static ram on it, that may well somehow connect to another FPGA; could be fun for a bit of fast access ram. Maybe one day parallella chips could have a special ram chip mounted on top of them, like the 'foxboard" processor had!

T.V.
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Re: the RAM

Postby trioflex » Sat Mar 09, 2013 7:17 pm

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