by theover » Sat Mar 09, 2013 3:11 pm
Dynamic ram isn't very fast concerning response time for random access patterns. So connecting another ram is of course possible provided there are sufficient pins left, but it isn\t easy (I've worked on it successfully in Open Source though), and especially, it isn't *that* fast, unless you know how to stride your access patterns and use a controller which can work with efficient page access and smart data streaming facilities of the latest generations of fast DRAMS.
Of course the FPGA has an amount of block- and random logic ram, which isn't in the gigabyte range though, but that is very fast ram. And it may well be feasible to connect some amount of static ram to the FPGAs external pins, provided there is still competitive static ram to be had. Also this is an easier and less delaying interface to create, but, like with all interface/controllers: it sounds easy, but testing the system so that it repeatedly over all kinds of versions and hardware component variations becomes reliable in the 1 error per lest say 100,000 hours op operation, may well be excruciatingly hard, when you don't know all the exact things going on. That's why hardware designers shouldn't be IT-ers, I'm sure. I have another (not expensive) FPGA board lying around, with a megabyte of static ram on it, that may well somehow connect to another FPGA; could be fun for a bit of fast access ram. Maybe one day parallella chips could have a special ram chip mounted on top of them, like the 'foxboard" processor had!
T.V.