Parallella Community

Will there be access to the ARM JTAG on the parallella board? According to the Zynq-7000 overview at there are two JTAG ports available that can be chained together or used separately, the ARM processor JTAG and the FPGA JTAG. I understand from the boot sources thread that the FPGA JTAG will be accessible. Will the ARM JTAG be available too, either chained to the FPGA JTAG or on a separate header? This would be very useful for low-level debugging, reflashing the bootloader etc.

Hi,
for me, i do not like the idea, that I could brick the board. I would e afraid to go anything near the possibility of bricking.
What I am missing too, is an access to a reset via PEC. I am not a HW engineer, but a SW engineer and actually working on Zynq7020.
What I need to feel safe regarding bricked boards, is the possibility to connect a XILINX plattform cable to a JTAG (via daughter board is ok) of the Zynq, connect it (XMD would be my choice) and reset the whole SOC and then have full access to the Zynq.
My inputs in XMD would be:
> connect arm hw
> rst
The Zynq SOC should be reset now.
Usually in this stage of boot the FPGA is not configured, I think.
If you have this access, anyone could do the unbricking via JTAG.

On the other hand, when you do not have this access, how is the parallella board being bootstrapped after production?
Zynq would be empty, I guess.

br
ESI