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Parallella Community • View topic - Parallella 2.0 Design Specifications

Parallella 2.0 Design Specifications

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

Re: Parallella 2.0 Design Specifications

Postby piotr5 » Tue Jun 23, 2015 12:51 am

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Re: Parallella 2.0 Design Specifications

Postby tnt » Tue Jun 23, 2015 6:24 am

Definitely DO NOT drop the samtec (well, you can change brand, but keep high density / high speed differential connectors). The ability to transfer huge amount of data in/out the board is critical

Also, the comment about the 7020 not being able to do the first filters for SDR just without any merit since the Ettus E310 uses the same 2x2 MIMO ADI9361 RFIC and uses a Zynq 7020 and all the logic and filtering fits in there. Also the ADI9361 includes internal DDC/DUC so you can even do the filters in that chip without involving the FPGA at all if you wanted to.
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Re: Parallella 2.0 Design Specifications

Postby briaeros007 » Tue Jun 23, 2015 7:42 am

Well, my bad If I offense anyone, it wasn't my intention.

-> I wasn't thinking of dropping the possible use case with high speed / high density connector. But for DIY, Samtec connector, let's be frank, are just unusable (difficulty to buy them, to solder them, and pretty costly too). (When I got my parella, I have found only a breakout board for _one_ connector ... at $80).
a daughter board to use these connector could be one way, but not a daughter board at $80. For less than $3 I've got a board with an atmega328 and all theirs pins usable, I will not pay $200 to use only 2 connectors when the parallela board is cheaper :)

-> I wasn't thinking of covering all gpio of the fpga for the "arduino-like". . But to cover gpio which aren't already in used, and in sufficient quantity that you could use for just more than 2 standard usage.
Parallela 2 board (or the daughter board) could also present the specific io which aren't populate on the board (as the 2nd GigE, 2nd USB, ...)

-> Concerning the capacity of the zynq for filtering. I appreciate the zynq 7020 and found the idea superb, but there are some area which are already taken into use for the connection of the ram, of the arm and of the epiphany.
In addition, my point was'nt saying that the "zynq is bad we must offloading things" , but "the possibility to add ADC/DAC and/or DSP "cheaply" could be great for those who want".
My example wasn't to your liking, and perhaps not true (there are only one way to be sure ;) ) , and I apologize for this.
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Re: Parallella 2.0 Design Specifications

Postby tnt » Tue Jun 23, 2015 8:45 am

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Re: Parallella 2.0 Design Specifications

Postby briaeros007 » Tue Jun 23, 2015 10:24 am

Thanks a lot for the procupine info and your well detailed posts.

It was what I wanted (but without finding) , and what I had in mind with my 0.1" connector.

I had no idea that the epiphany was using so little space (witthout the hdmi thing, doesn't it ?)

Now, let's hope that digikey will not kill me with transport fee when they've got the board available (no radiospares agreement on this? )
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Re: Parallella 2.0 Design Specifications

Postby tnt » Tue Jun 23, 2015 11:31 am

Yes, the above results are for a headless configuration. Unfortunately the FPGA design with HDMI is based off an older version of the fpga code and only in ISE not Vivado. Personally I don't really care about HDMI so I don't mind, but if you want HDMI output, that's annoying, you'd have to port it forward yourself.
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Re: Parallella 2.0 Design Specifications

Postby dobkeratops » Sun Jun 28, 2015 7:12 pm

Does anyone know off hand how much of the basic 7010 version is used both with & without HDMI support
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Re: Parallella 2.0 Design Specifications

Postby TomKeddie » Fri Jul 24, 2015 8:27 pm

I've done a board with Arduino pinout on the underside.

viewtopic.php?f=11&t=3081
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Re: Parallella 2.0 Design Specifications

Postby niqingliang2003 » Fri Aug 14, 2015 7:50 am

can we have kicad version layout???????
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Re: Parallella 2.0 Design Specifications

Postby dancer42 » Thu Aug 27, 2015 8:42 pm

when you consider the spec. for 3.0 you might think about splitting the standard to include 1 for interfacing clusters to other clusters and pc's and 2 to be stripped of all io but 1 usb port for plug in support of small clusters the first can be a computer or smart interface for a pc and the second would streamline the cost of anding cluster power.
the second with an appropriate driver could add much needed speed to older laptops and desktops that with both board types would be scaleable.
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