Parallella 2.0 Design Specifications

[aolofsson]

This may come as a surprise, but with the Parallella 1.1 now ramping up production we are already in a rush to get Parallella 2.0 out the door!
The DDR3 part that we are using on the board was unfortunately "End of Lifed" last August and we just placed our last time buy. This means that the total number of Parallella-1 produced will be limited to ~20,000

Unfortunately there are no pin compatible parts so we need to respin the board. This work is already in progress, but we want to reach out to you to get feedback regarding suggestions for changes to the board. Here's the plan as it stands, please respond to this thread to approve/disapprove these changes and to add your own thoughts about features needed. We are trying to keep these changes as small as possible to minimize design cost, compatibility, and risk.

Change #1:
Change DDR memory design to use 2 16-bit wide DDR memory chips instead of a single chip (twin die) 32-bit wide chip.
Why: 32-bit wide interfaces no longer supported well.

Change #2:
Use a standard USB host port connector (major change!)
Why: More mechanically sound and removes need for annoying adapter cable.

Change #3:
Remove the 2nd USB chip.(next to the ethernet RJ45). Connector stays for power delivery.
Why: Questionable feature to start with and we don't have the resources to support the feature. Connect with ethernet, Wifi, GPIO.

Change #4:
Move the tall 100uF caps to the bottom side
Why: Allow for more efficient heat sinks for the Epiphany/Zynq

Change #5:
Move the mounting hole 5V jumper pin
Why: Mechanically wrong placement

Change #6:
Move the reset pin
Why: Get out of the way from the heatsink

Change #7:
Move the diodes to central location
Why: Makes for easier case design (ala Raspberry Pi)

Change #8:
Change the UART_TX input pull down to "pullup"
Why: Verified to be more robust to noise (still verifying..)

Change #9:
Change Epiphany reset signal to 1.8V
Why: Currently being driven from a 2.5V bank..which is not that healthy long term.)

Any and all inputs are welcome! Speak now or forever hold your peace.

Andreas

[hsauro]

Make it easier to tap the 5v supply to power a fan. Currently soldering is required.

[aolofsson]

Good point. Thanks!

Change #10:
Add 5V/GND 0.1" pin-pair for 5V fan
Why: Board runs hot and we want to make it simple for people to install small footprint fans.

[9600]

[Transcendental]

One thing that I've wondered about given the Parallella's trouble dissipating heat: other than the ironically-named "Coolness Factor", is there any reason that the board needs to be as small as a credit card? Might increasing the size of the PCB be a good idea? (cf. Mentor Graphics' FloTHERM CFD software)

[Gravis]

wishlet:
* holes to secure a heatsink
* microusb in so it can be used as a usb 3.0 device connected to a PC. <-- seems like a really good idea
* faster ethernet connection
* minimalistic version that is a PCIe card. (i can dream, right?)

[Janos]

[shodruk]

All the connectors should be attached with through-hole connections.

[LinuXperia]

I would like to see a easy possibility to expand Parallella with more Gigabit Ethernet Ports.
This will allow Parallella to be used as a Network Device and will provide a alternative to NetFPGA Boards.
Only one Gigabit Ethernet Port is quite limiting.

Beside this one very Important extension is also Mass Storage Possibility like attaching a Terrabyte SSD to Parallella over Sata as a example. Having a Parallela Board that can do a lot of Computation with the possibility to store this Mass Results inside the Parallel Tasks would make Parallella much more usable.

Ofcourse for such a Parallella Board i am willing to pay also a higher Price than the 99 USD.

[mhonman]

option 1: (preferred) add a PEC-W connector for the on-board Epiphany's West eLink so that a group of Parallellas can form the east edge of a larger matrix of Epiphanies
option 2: (only 2 external links) - provide expansion connectors for North and West rather than North and South so that Parallella can occupy the SE corner of that bigger parallel processing mesh.