FPGA Source / Project Repository

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Re: FPGA Source / Project Repository

Postby frank_buss » Thu Jul 03, 2014 11:22 pm

tdam wrote:frank,
I created a simple register with an AXI lite interface as well. Then I have successfully reprogrammed my fpga design. However I'm having some issues to access my register, I was trying to do it mapping the physical address of my register to the virtual address through the mmap, however every time that I tried to access it, it freezes my parallella. Can you give me a little help on how you have written your driver, since my approach doesn't seem to work?
thank you

This is my driver:
https://github.com/FrankBuss/parallella ... er/sampler
You can compile it on the Parallella, but you need the kernel sources, e.g. as explained here:
viewtopic.php?f=48&t=1230
Execute "make modules_install" at the end, so that the right directory is created for the Makefile. sampler.c is the driver. You can call "insmod sampler.ko" to load the driver and server.c is a (unfinished) example how to use it.
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Re: FPGA Source / Project Repository

Postby tdam » Fri Jul 04, 2014 4:42 am

I will try it tomorrow, really appreciated it.
Thanks a lot, Frank =)
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Re: FPGA Source / Project Repository

Postby shodruk » Sat Oct 11, 2014 8:45 pm

Hi Fred,

I've found some bugs in the parallella-hw project.

In parallella_7020_hdmi:
XPS > Clock Generation > PL Fabric Clocks > FCLK_CLK1 is set to 152.
I changed it to 125.

In parallella_7010_hdmi, parallella_7020_hdmi:
XPS > Bus Interfaces > clock_generator_0 > (right click) > Configure IP > CLKIN: Input Clock Frequency: 0 (changed to 100000000)

CLKOUT0: Required Frequency: 0 (changed to 12288135)

After changing these parameters, I generated the bitstream, and I've got HDMI sound working!! Yay!! :D

(I tested with parallella_7020_hdmi.)
Shodruky
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Re: FPGA Source / Project Repository

Postby shodruk » Wed Oct 15, 2014 7:37 pm

I tried to build parallella_7010_hdmi, I got these errors.

[Pack 2310] Too many comps of type "MMCME2_ADV" found to fit this device.
[Map 237] The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as their packing might not have been completed.

Reports->Map Report
Number of MMCME2_ADVs: 3 out of 2 150% (OVERMAPPED)

I think this is because Zynq7010 has only 2 MMCMs (Zynq7020 has 4).
So I removed clock_generator_0 and connected FCLK_CLK3(40MHz) to spdif_data_clk in axi_spdif_tx_0.

Open system.xmp with XPS,

System Assembly View > Bus Interfaces >
right click on the clock_generator_0, Delete Instance, "Delete instance but do not remove the nets"

System Assembly View > Ports >
expand axi_spdif_tx_0,
click on the "Connected Port" next to the spdif_data_clk,
connect to "processing_system7_0" : "FCLK_CLK3", OK,

exit XPS,

PlanAhead > Design Runs > select "synth_1",
Click "Reset Selected Runs" button, "Reset",

Then generate bitstream.

Reports->Map Report
Number of MMCME2_ADVs: 2 out of 2 100% :D

And modify audio_clock in the devicetree.dts,
clock-frequency: 0xbb8000 to 0x2625a00

devicetree.dts

Code: Select all
audio_clock {
 compatible = "fixed-clock";
 #clock-cells = <0x0>;
 clock-frequency = <0x2625a00>;
 linux,phandle = <0x9>;
 phandle = <0x9>;
};


And there seems to be no need to use ".asoundrc" with this bitstream.

rm ~/.asoundrc

Because I don't have a 7010 board, I haven't tested it on a 7010 board yet,
But I tested on a 7020 board with this settings, it works fine and HDMI sound is working! :D
Shodruky
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Re: FPGA Source / Project Repository

Postby Len » Sun Oct 19, 2014 7:41 pm

Super catch.

How do we get these changes in the current build?
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Re: FPGA Source / Project Repository

Postby FHuettig » Mon Oct 20, 2014 3:08 am

Hi Shodruky / Len,

Sorry I haven't had a chance to look this over before now, too many first-priorities! The 7010 problem is very puzzling because I have built and used that code and project as-is on hardware, I don't see any changes to the repository. The audio issue is puzzling too but somehow I must have been using the old (pre-"me") bitstreams when I had audio working and only noticed the problem after we updated the kernel and lots of other things. I'll check that out too.

I'll be sure to go over these items in detail early this week and update the repository to incorporate the fixes.

Thanks for the detective work Shodruky!
-- Fred -- Hardware Guy --
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Re: FPGA Source / Project Repository

Postby shodruk » Mon Oct 20, 2014 1:34 pm

Thanks Fred,
I'm using kernel-hdmi-140603.tgz (not the latest one on the linux kernel repository)
Shodruky
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Re: FPGA Source / Project Repository

Postby FHuettig » Wed Oct 22, 2014 4:09 am

Hi Shodruky,

shodruk wrote:In parallella_7020_hdmi:
XPS > Clock Generation > PL Fabric Clocks > FCLK_CLK1 is set to 152.
I changed it to 125.

I'm curious why you think that is an error? When I got the project that clock was set to 200MHz and it would fail timing, I wanted to keep it as high as possible so as to keep the latency down for video data. Timing showed 152 was OK, but because of the limited divider values it comes out to 142 on the hardware. For 1080p60 we need to keep up with a pixel rate of about 150 pix/sec (not sure if it's 16b/pix or 24b/pix coming over the DMA, but either 125 or 150 should be fine).

Did changing that value to 125 have any effect on the system?

shodruk wrote:In parallella_7010_hdmi, parallella_7020_hdmi:
XPS > Bus Interfaces > clock_generator_0 > (right click) > Configure IP > CLKIN: Input Clock Frequency: 0 (changed to 100000000)

CLKOUT0: Required Frequency: 0 (changed to 12288135)


That's very strange, I see it was that way when I got the project (6 or 7 months ago now!) and I never noticed. Somehow I never correlated the lack of sound with the bitstreams I was generating, shame on me! I'm sorry and thank you for finding this.

Curious: why 12,288,135, shouldn't it be 12,288,000 or 48ks/s * 256? It should be possible to get exactly 12.288 from 100MHz in with an MMCM.

shodruk wrote:After changing these parameters, I generated the bitstream, and I've got HDMI sound working!! Yay!! :D

Yay indeed! I've made the change to my project (the audio clock, not the 152->125 AXI clock change, unless it matters) and as soon as I can test it out I'll update the repository.

shodruk wrote:I tried to build parallella_7010_hdmi, I got these errors.
[Pack 2310] Too many comps of type "MMCME2_ADV" found to fit this device.

OK, I guess the first error explains the second. With CLKIN/CLKOUT set to zero, the clock generator module was empty, so no error. It's not completely clear to me why this fails, since each CMT has both an MMCM and a PLL, and we only need two MMCMs for the pixel clock and audio sample clock, and a PLL should be OK for the Epiphany clocks. Maybe the epiphany one is instantiated specifically as an MMCM. More to look at...

We should have an extra clock output available from the PS rather than tying the audio to an AXI clock, but we may not have fine enough resolution on that to get to 12.288, the closest I seem to get is 12.345679 (cool number!?).

Best,
Fred
-- Fred -- Hardware Guy --
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Re: FPGA Source / Project Repository

Postby shodruk » Wed Oct 22, 2014 11:41 am

Hi Fred,

I first tried to build parallella_7020_hdmi, I got this error.
(without modification, I followed your instructions)

[Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [/home/---/parallella-hw/fpga/edk/parallella_7020_hdmi/__xps/pa/_system_synth.tcl]


cat /home/---/parallella-hw/fpga/edk/parallella_7020_hdmi/platgen.log

ERROR:EDK:3900 - issued from TCL procedure "zynqconfig_do" line 34
processing_system7_0 (processing_system7) - MHS file editing for Zynq related
parameters is not allowed. Please use Zynq tab in XPS for PS configuration.
Value of parameter C_FCLK_CLK1_FREQ (142857136) in MHS conflicts with the
setting in Zynq tab. Value of C_FCLK_CLK1_FREQ should be 142857152
ERROR:EDK:440 - platgen failed with errors!


So I tried to fix the clock setting.

"125MHz" and "12288135" are from the reference design of xcomm_zed.

https://github.com/analogdevicesinc/fpg ... system.mhs

But I found that the clock of the vdma in the reference design is "100Mhz" today.

I will try it later.
Shodruky
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Re: FPGA Source / Project Repository

Postby shodruk » Thu Oct 23, 2014 12:34 am

Thanks Fred, I understand.
The CLK1_FREQ issue is due to ISE.
I restored the CLK1 setting (to 152), generated bitstream, it succeeded.

I found my 40Mhz clock hack is not reliable, some monitors worked, but some didn't.

I tried the PLL mode of the clock_generator_0, it works fine!
Also I generated the 7010 bitstream and it completed successfully!


Summary of the Modification:

XPS > Bus Interfaces > clock_generator_0 > (right click) > Configure IP > CLKIN: Input Clock Frequency: 0 -> 100000000

CLKOUT0 > Required Frequency: 0 -> 12288135

CLKOUT0 > Required Group: None -> PLLE0

".asoundrc" is still necessary.

Please ignore other modifications.
Shodruky
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