FPGA Source / Project Repository

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Re: FPGA Source / Project Repository

Postby tnt » Thu Jun 12, 2014 12:21 pm

From reading the u-boot code, it seems to be done this way for the RAM because the ram is actually auto-detected (with the #define just being the maximum detect range).

The only things that seems to be patched in create_fdt() in arch/arm/lib/bootm.c are the memory node and the ethernet mac address.
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Re: FPGA Source / Project Repository

Postby greytery » Thu Jun 12, 2014 5:30 pm

OK. Thanks for following me down this rabbit hole with a lamp. :D That was fun!
I was expecting that shared memory could be more easilly and flexibly configured. But not so sure that this is productive now:-
- The U-Boot config controls the allocation of shared memory allocation of 32MB.
- To change that amount involves recompiling the whole bootloader. :cry:
- I'm in favour of minimal change to U-Boot board config to minimise the U-Boot Git hassle.
- The "memory" allocation in the device tree should be tidied/removed to avoid confusion (- or recognised by U-Boot which I can't see happening).
- Will update the thread on 'increased shared memory', maybe skin the cat another way.

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Re: FPGA Source / Project Repository

Postby aolofsson » Thu Jun 12, 2014 5:42 pm

fyi..the u-boot/kernel shared memory hack was just a temporary solution, we are now working on something more flexible and way coooler.:-)
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Re: FPGA Source / Project Repository

Postby greytery » Thu Jun 12, 2014 6:26 pm

aolofsson wrote:... just a temporary solution, we are now working on something more flexible and way coooler.:-)
Andreas


Aw - please tell. Pretty please. :?:
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Re: FPGA Source / Project Repository

Postby frank_buss » Tue Jun 24, 2014 9:20 pm

I can generate the bitstream with the PlanAhead tool, but I get errors when I try to use the Xilinx Platform Studio and system.xmp (both with the 7020 HDMI projects)
ERROR:Pack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource
requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not
be reflected accurately as their packing might not have been completed.

I'm new to the Zynq IDEs, but I would like to implement my own VHDL module, which should read and write from the DDR RAM by DMA (e.g. for a DAC or ADC). I found a nice description how to do this ( http://www.fpgadeveloper.com/2014/03/us ... ngine.html ), but I can't follow it when I can't even generate the bitstream with the original non-modified project.

I read somewhere that Adapteva is planning to migrate to Vivado, so maybe woudn't make sense to fix this problem. Will it be possible to use Vivado with a free WebPack licence, too?
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Re: FPGA Source / Project Repository

Postby FHuettig » Tue Jun 24, 2014 9:32 pm

frank_buss wrote:I can generate the bitstream with the PlanAhead tool, but I get errors when I try to use the Xilinx Platform Studio and system.xmp (both with the 7020 HDMI projects)
ERROR:Pack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource
requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not
be reflected accurately as their packing might not have been completed.

I'm new to the Zynq IDEs, but I would like to implement my own VHDL module, which should read and write from the DDR RAM by DMA (e.g. for a DAC or ADC). I found a nice description how to do this ( http://www.fpgadeveloper.com/2014/03/us ... ngine.html ), but I can't follow it when I can't even generate the bitstream with the original non-modified project.


Hi Frank, are you sure you've selected the right device and package in XPS? The design does fit, pretty easily, even in the 7010, so I have to think there's an incorrect setting when you use xps. Usually I open xps by double-clicking on the system.xmp in PlanAhead, so there may be some parameters that get passed that way but not if you open xps directly. Is there a reason you don't want to start with PlanAhead? Can you tell me exactly what steps you took to get those errors?

frank_buss wrote:I read somewhere that Adapteva is planning to migrate to Vivado, so maybe woudn't make sense to fix this problem. Will it be possible to use Vivado with a free WebPack licence, too?

Yes, I'm pretty sure the 7010 and 7020 devices are included in the WebPack for Vivado.

-Fred
-- Fred -- Hardware Guy --
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Re: FPGA Source / Project Repository

Postby frank_buss » Wed Jun 25, 2014 12:22 am

I was reading this blog: http://www.parallella.org/2014/05/13/fp ... expansion/ and it says "The FPGA projects are built using the PlanAhead tool and the free-of-charge ISE WebPACK Design Software is sufficient.". The article doesn't mention XPS and I could even change the GPIO implementation. But for more complex implementation beyond a blinking LED on a GPIO pin, I need XPS.

So I started XPS from PlanAhead with a double click to "Project Manager->Sources->Libraries->Design Sources->Embedded Design Sources->system" (these multiple nested panels are confusing). I tried a simpler tutorial ( http://www.zedboard.org/content/creatin ... peripheral ) and I could create my own VHDL module. "Design Rule Check" worked, I closed XPS, but how do I update the parallella_z7_top.v file? Looks like it has some auto generated signals in the "AUTOWIRE" section. I guess I can do it by hand, but this is error prone (especially in Verilog :) ) when I add and remove more peripherals.
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Re: FPGA Source / Project Repository

Postby FHuettig » Wed Jun 25, 2014 4:59 am

frank_buss wrote:I started XPS from PlanAhead with a double click to "Project Manager->Sources->Libraries->Design Sources->Embedded Design Sources->system" (these multiple nested panels are confusing). I tried a simpler tutorial ( http://www.zedboard.org/content/creatin ... peripheral ) and I could create my own VHDL module. "Design Rule Check" worked, I closed XPS, but how do I update the parallella_z7_top.v file? Looks like it has some auto generated signals in the "AUTOWIRE" section. I guess I can do it by hand, but this is error prone (especially in Verilog :) ) when I add and remove more peripherals.


At some point you do have to modify the top level if you've added anything in xps that wants to connect to the outside world. That file (parallella_z7_top.v) is written by hand, but it's not complicated, mostly just routes things from the system module (xps) to external pins, through the gpio module in the case of gpios, and of course connects two AXI interfaces to the epiphany logic but you can leave that alone unless you need direct access to the epiphany.

The AUTOWIRE stuff, and other AUTO* entries you may see, are from the verilog mode of emacs which I highly recommend. That mode automates a lot of the drudgery and makes it much less error-prone, but it is simply a tool provided by the editor, it's not part of the language or anything that the Xilinx tools depend on or even notice (they are specially-defined comments). Specifically, AUTOWIRE is a way to have the editor insert wires for all the output signals from instantiated modules, in particular those modules that use AUTOINST to automatically pull the port definitions from the external module. If you add ports to the system module you just add them to the instance in the top level and connect those signals as needed, you can ignore all the AUTO stuff unless/until you want to use that tool.

I can't quite tell from your description if you are still getting errors during the build, or have you gotten past that and now want to do more sophisticated work that requires changes at the top level?
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Re: FPGA Source / Project Repository

Postby frank_buss » Wed Jun 25, 2014 11:50 pm

Thanks, the Emacs feature sounds interesting.

Finally I managed to add a simple register based entity (with an AXI lite interface) and I wote a Linux kernel driver to map the register memory with request_mem_region and ioremap_nocache. I can write and read the registers, so XPS and PlanAhead works. When I use the non-modified bitstream, the driver aborts with an "imprecise abort" (I guess it detects somehow that there is no acknowledge from the AXI bus), so this is a proof that the entity was indeed synthesized in my design.

But I don't like the Xilinx tools. Sometimes PlanAhead crashes with an access violation and when I restart it, it can't generate the bitstream anymore, because it left read-only files from the last run. Or sometimes the netlist is not updated and I have to do it manually in XPS. The Altera tools with NIOS etc. look more stable and are easier to use. Well, the Zynq is still a nice chip, so I have to live with it. I guess Vivado will be all new and better, with many novel bugs :twisted:
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Re: FPGA Source / Project Repository

Postby tdam » Thu Jul 03, 2014 9:47 pm

frank,
I created a simple register with an AXI lite interface as well. Then I have successfully reprogrammed my fpga design. However I'm having some issues to access my register, I was trying to do it mapping the physical address of my register to the virtual address through the mmap, however every time that I tried to access it, it freezes my parallella. Can you give me a little help on how you have written your driver, since my approach doesn't seem to work?
thank you
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