epiphany chip emulator

[EggBaconAndSpam]

Also:
Your implementation of B<cond> (16) is missing sign extension of the immediate offset.

ASR (imm) 16bit: RD = (RN >> SIMM) | (RN << (32 - SIMM)); This is bollocks, you are essentially mapping the low bits of RN to the high bits of RD.
Should rather be RD = (signed int) RN >> SIMM;
However, strictly speaking, '>>' is implementation defined for signed types. GCC uses the arithmetical variant, so you should be fine.
Same goes for ASR 16bit (no imm).

All FPU opcodes:
BV else {BV = 0} is missing, it is NOT STICKY (BVS is...)!
BZ = !RD; might be problematic, !float is illegal in the C main standard, though might be ok in a later standard.
use BZ = !(RD == 0f) for increased verbosity.
Also, even though we are pretty much talking about pseudo code, you would have to cast the registers involved to float.

All secondary IALU instructions:
BZ = !(RD&0x7FFFFFFF), have a look at the reference manual.

FIX,FLOAT,FABS: no RM register involved, documentation error.

MOVFS: "move _from_ special register", should be RD=read_memory32(core, offset + RN);

[Gravis]

[EggBaconAndSpam]

In that case, you would have to decide whether you want your emulator to work on a cycle-level, so that pipeline stalls and all that good stuff becomes an issue, or not.
Implementing penalties does imply low-level emulation, however, your current design does not support it.
You would actually need to simulate the pipeline stages and so on, as well as the eMesh on a cycle-by-cycle level.

[Gravis]

[Gravis]

[EggBaconAndSpam]

I did not intend to sound mean, ironic rather. Sorry for that.

Regarding the pipeline thing:
Instructions don't actually complete in just one cycle.
A LDR instruction takes 6 clock cycles, from the opcode being read, to the eventual writing of the register.
In 2 of these cycles, the result register is claimed, that is, can't be accessed by other operations in the meantime.

As a result, the sequence LDR RX,RY,RZ; ADD RA,RX,RX; causes a pipeline stall, ADD tries to access RX in stage RA (register access, loading of the register args) whilst it still is being claimed by LDR, in stage E1.
This, effectively, causes a one cycle penalty (see section 7.9).

With FPU instructions this gets even more irritating, as most of them claim their target register for 5 cycles...
Actually modelling the cpu to that degree would require modelling of the pipeline and its stages. You may want to avoid that.

As for cycles and stuff, the cpu actually has 8 parallel pipelines (times two, for dual-issuing) in order to achieve 1 cycle per command.
Whilst it makes for a high throughput, the individual latency of commands does not decrease. (If that makes sense)

"The CPU has a static dual-issue architecture that allows two instructions to be executed in parallel on every clock cycle"
The term "executed" is used loosely, in this case issueing is actually meant instead.

[ysapir]

[Gravis]

@yaspir

is one cycle equal to one stage of the pipeline?

[ysapir]

Gravis,

A pipeline stage and a cycle are two different concepts (as described above), so they cannot be "equal". What you probably mean to ask is whether a pipeline stage takes one cycle to complete. The answer yes, if there are no stalls (either for the instruction at that stage, or from former instructions in farther stages). If there are stalls, then the time (cycles) it take for a stage to perform is 1 + # stalls.

The time it takes for an instruction to complete is the length of the pipeline + # of stalls on its way down the pipe. Obviously, there could be as many instructions in the pipe as pipeline stages, so if there are no stalls, the throughput is one instruction per cycle.

[EggBaconAndSpam]

On another note: This won't work, either.
SIMM = get_num(op, 8, 7) | (get_num(op, 15, 1) << 31);

Again, just use a cast to signed, or this:
RD = RN >> SIMM;
if(RN & (1<<31)) RD |= 0xFFFFFFFF << (32 - SIMM);

Have a look at http://en.wikipedia.org/wiki/Two's_complement , sign extension just maps a negative value of a lower bit size to a higher bit size, keeping its arithmetical value.

Also, it should be get_num(op, 8, 8);