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Parallella Community • View topic - Timers and Barriers
Page 1 of 1

Timers and Barriers

PostPosted: Mon Jul 21, 2014 8:34 pm
by sebraa
Hi,

in my current code, I use barriers for synchronization as well as the event counters to measure the clock cycles. The main idea is that at the beginning of the loop, I start the counter and at specific times inside the algorithm I only read the values into an array (to make sense of it later).

The approach works fine, but after the first barrier, some counters (depending on something, 3 to 6 cores) get stuck. Restarting them doesn't help. If I always stop/start the timers, they don't get stuck. All 16 cores run the exact same SREC file.

Is any interaction between barriers and event counters known? Why could a CLK-counter just stop counting?

Is there any information about barriers around? What is the overhead using them, I measured some 600 clocks when all cores are synchronous, but when running 5-6 barriers directly after each other, the timers only show zero differences (since reading a timer takes about 26 cycles, something is wrong there).

Best Regards,
Sebastian

Re: Timers and Barriers

PostPosted: Wed Jul 23, 2014 11:45 am
by timpart
The only documentation I'm aware of for the barrier functions is in the SDK manual. The source code is also .

The barrier code doesn't look as though it has anything to do with clocks.

For people to help you further you may need to post source code extracts, such as the declaration of the barrier array and how it is initialized and the barrier invoked. Also how you are setting up the clock(s) and using them.

Tim

Re: Timers and Barriers

PostPosted: Fri Jul 25, 2014 5:41 am
by notzed
The barriers don't use timers at all and neither should anything else in elib. Presumably the timer isn't just underflowing either. Unless it's changed since I last looked the barrier implementation in elib just uses shared memory so depends on cross-core latency. Relative to "on-core time" it's a bit expensive but nothing unreasonable.

I vaguely recall there were some bugs in the compiler at some point to do with the fpu mode switching ... which might affect the timers since they are configured using the same register. Short of some other major bug (like pointers going awry) that is all I can think of. Having the timers in the same config register wasn't ... wise.

To check it you'd have to look at a disassembly of the binary.

Re: Timers and Barriers

PostPosted: Fri Jul 25, 2014 12:58 pm
by sebraa

Re: Timers and Barriers

PostPosted: Sat Jul 26, 2014 2:25 am
by notzed

Re: Timers and Barriers

PostPosted: Mon Jul 28, 2014 1:48 pm
by sebraa
If I find the time, I will try to reproduce the problem. But thanks for the help.

I take much care in the few pointers I use (mostly just two memcpy()-calls to the shared memory plus array-passing), and I use -Wall to make sure they match, so the pointer usage should be fine. Interrupts are not used, neither is DMA or any other hardware-feature.

Re: Timers and Barriers

PostPosted: Fri Jan 16, 2015 10:45 pm
by sebraa

Re: Timers and Barriers

PostPosted: Mon Nov 28, 2016 4:22 pm
by vanchiramani
Dear Sebraa

Did you fix this problem?

Any help really appreciated!

- V Vanchinathan

Re: Timers and Barriers

PostPosted: Tue Nov 29, 2016 9:56 am
by sebraa
No. There is a problem somewhere, but instead of hunting it down, I work around the problem instead. Basically, I only measure smaller amounts of code, measure while developing and whenever I get unexpected values, I keep in mind that the measurement itself could be wrong.

Re: Timers and Barriers

PostPosted: Tue Feb 21, 2017 6:08 am
by GreggChandler
I believe that I have found a problem with the uniformity of mutex acquisition. If barriers use mutex's in their implementation, I would expect problems based upon what I have seen. viewtopic.php?f=13&t=3987