Parallella Community

Can I access the CAN bus on any of the GPIO pins? I have been unable to find where the pin functions are defined in the multitude of pdfs.

Thanks,
David

The one you need to look at is the Zynq reference manual. It should be possible to output the hard coded CAN interface int he Zynq on the GPIO pins by just routing the MIO pins, but others on this forum might know better.

(see figure 1.1, also see pg52)
http://www.xilinx.com/support/documenta ... 00-TRM.pdf

Andreas

Thanks Andreas. I had the manual, I just hadn't found that page!

Looks like there is a lot of choice where the two CAN engines can be connected.

I am unclear how the PEC_FPGA pin numbering corresponds to that table. I will peruse the schematic some more.

David

It looks like I can repurpose the UART RX and TX. However, it also appears that the CAN siganls can be directed through the EMIO to GPIO pins, but I cannot figure out how one goes about doing that.

David

Probably best to leave the UART RX/TX alone. The EMIO configuration would be done through the Xilinx design planner tool (GUI "click and fill"). The Parallella reference design is a good starting point.

http://www.adapteva.com/white-papers/pa ... ce-design/

Andreas