A 4-way cluster backplane

[timpart]

[ticso]

To correct myself: it is 8x 64 core.
The FPGA way sounds difficult if possible at all and I doubt it can be very fast as AFAIK there are not that many io and no serdes.
Even with just north/south interconnection it is tricky with the zynq <-> ecore communication as a zynq can write to any ecore, but only read from direct connected and ecore can only write to local connected zynq.
In my project I don't need any parallella interconnection at all, but I want to support it with my board layout - just in case.
And I want some raw NAND flash chips for fast storage - will decide later depending on PL space and IO required if I connect to zynq or elink via extra FPGA.

[Sundance]

[9600]

Thanks for sharing your ideas for this board, Flemming!

As well as the dual vs. quad Parallella design decision, I'd also like us to consider the options of:

P00xA: Budget board

Some of the FPGA pins routed to 0.1" breakout, with others either hard-wired between Parallella boards or routed via a smaller FPGA or similar. Meaning that you don't need to buy another module to add breakout and you get at least some high-speed FPGA interconnect, if not entirely flexible.

P00xB: Premium board

As Flemming described and with those additional high-speed connectors that carry PEC_FPGA. Enabling a module to be added with an FPGA, for routing signals between each Zynq PL and to implement PCI-E interface etc.

Just to be clear the plan is that this board(s) would be open source hardware too.

Thoughts?

Cheers,

Andrew

[Gravis]

[Sundance]

Hi,

Me - and "Only Another" - thought that PCI Express would be useful on a Carrier, so let forget about that idea for now and go back to something much simpler and less cost, as original asked for.... - and make it a 2-way, to reduce the cost of PCB and number of connectors, that can scale to ANY number (given enough desk-space)

The attached drawing is a Carrier for 2x Parallalla's and connectivity is hopefully clear, but allow me to add:

1. PEC_North <> PEC_South via tracks. These will run at full eLink speed

2. PEC_Link_North connector can mate with PEC_Link_South Connector on a SECOND P002, populated with 2x Parallalla's - etc.

3. PEC_Link_South connector can mate with PEC_Link_North Connector on a THIRD P002, populated with 2x Parallalla's - etc.

4 The PEC_Link Connector is a 60-way connector by Samtec - LSHM - http://www.samtec.com/technical-specifi ... aster=LSHM - and designed for higher speed than eLink. They click and locks. Lovely!

5. All signal from PEC_FPGA to a 0.1" spaced "Bread-Board" area, that COULD be populated with a 0.1" Header, but left for User to add, as might want to SOLDER wires; Might want to make Tea, etc.! - or might never want to use.

6. All signal from PEC_POWER to a 0.1" spaced "Bread-Board" area, that COULD be populated with a 0.1" Header, but left for User to add, as might want to SOLDER wires; Might want to make Tea, etc.! - or might never want to use.

7. ATX-PSU Connector is to connect to 5V source to power BOTH Parallalla's, using the Mounting Holes Input power. It would ALSO be possible to use the 5V Barrel with a sufficient PSU Brick on one of the Inputs, but not more than 1x P002, so multiple P002s would require common 5V

8. Will 8-layers and impendence-match PCB (150mm x 105 mm) to make the eLink able to work @ full speed.

We have to do a batch of 100x boards to make this a $99.99 adventure and Sundance are quite happy to bank-roll the development cost and MOQ investment, IF any interest. Any purchase order would be with PayPal or Debit/Credit Card on a secure Web-site and no money taken until P002 was shipped. I did see the idea of a "Kick-Starter" for this, but much easier potentials to simple order on requirements.

The price would be closer to $75.00 for a batch of 250 and then it will not really get a lot cheaper unless we were into the 10000's!

Andrew (#9600) said it might be possible to use this Support Forum as a way to get a poll of interest and I will leave that with him.

I am surely open for better ideas as well, although I can't think of anything to remove anymore, expect the second Parallalla, to make it a One-Way Carrier. That IS an option...

Do not be shy... - speak-up, please

... - ups... - PDF not allowed. - will try to save a JPG

[LamsonNguyen]

I am interested and I'm sure those who pledged for 2+ boards would be interested as well.

[Gravis]

[ysapir]

[Sundance]

#LamsonNguyen: Glad you liked it. Thanks

#Gravis: You were NOT "The Another", as you clearly stated that you had own facilities to build a board with PCI Express and 64x Core Epiphany. You are going to find it interesting to connect to the 16-lane PCI Express Bus of your PC directly. - but a good idea, as Epiphany is effectively a "Co-Processor" as explained here - viewtopic.php?f=23&t=429&p=2661#p2661 - and hence why my initial idea was to add another FPGA, etc.
That will be for another day

#ysapir: The Bittware offering is truly impressive and an inspirations. Thanks for sharing.

Anybody else got comments about the idea of a simple Carrier for 2x Parallalla's?
Should it be 1x Carrier that scales like the current idea?