Altera HSMC

[fuzz]

Hi,

I made a DIY HSMC Paralella carrier to connect one of the eLink interfaces to an Altera Cyclone V FPGA.

pcbs.jpg (46.74 KiB) Viewed 19841 times

phsmc.jpg (47.86 KiB) Viewed 19841 times

I got the mating connectors directly from Samtec, HSMC Samtec from DigiKey, PCBs made by Bay Area Circuits (designed in DipTrace). I got a desktop stencil for the top layer from BAC to apply solder paste and ran it in a T-962A reflow oven. The bottom HSMC connector I carefully applied paste by hand and did a second reflow pass. This was actually my first project with the oven, and was surprised how well it turned out. It did take a few attempts to get it right.

I've been working on some Verilog to communicate with the Epiphany. I'm fairly new to HDL, so any pointers would be great! I currently have a basic receiver/aligner working that's up on GtHub https://github.com/wtfuzz/epiphany_altera

I seem to be updating and checking twitter more these days instead of forums, so if anyone's interesting in following along: @inet_ntoa

Cheers!

[9600]

Nice work!

Is there a particular application involving the Altera board? Or is this just for fun?

Cheers,

Andrew

[fuzz]

This is currently just for fun, with the goal of finding new applications. I'm interested in what capabilities adding I/O flexibility to the Epiphany will bring. I realize some of this exists with the Zynq, but I've already become somewhat familiar with Alteras tools. The workflow seems easier as well with an external FPGA as you can reprogram the target without disrupting the Linux host on the Zynq.

This C5G has 256MB of LPDDR2, hdmi, 24 bit audio, usb uart, some GPIO and a number of 3.125gbit transceivers. My main interest is writing modules that could be directly interfaced via eLink. For example SGMII gige PHYs connected to the transceivers, with MACs in the FPGA that could be setup via epiphany cores and do packet DMA into the mesh for parallell packet processing.

I've been envisioning the model of tiny performant CPUs working together for a while rather than the current few big core model. I think to support this model the peripheral hardware needs to be rethought as well. In the Ethernet case, imagine the hardware filling many tiny rings instead of one global RX ring for example, eliminating traditional locking of shared buffers.

[9600]

That does sound interesting and you could obviously imagine networking folks getting excited by the idea of such a model. Perhaps people working on high-frequency trading applications also.

Looking forward to following your progress with this

Cheers,

Andrew

[MiTfreak]

Is anyone planing to do something similar with FMC connector? There i a lot of
daughter cards with FMC, and my only problem with parallela is that there are
no daughter cards (I am especially interested in something like FMCOMMS cards
from analog devices). I saw that there is design of RF daughter card, but none
is producing it still. Parallela could have nice future but without daughter cards
it will be hard to apply it.