Daughter card proposal

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Daughter card proposal

Postby Folknology » Tue Feb 19, 2013 11:40 am

I have spent quite a bit of time over the years designing interfaces and expansion modules for various projects which has provided me with some really interesting experiences on both sides of the fence, I have also often had thoughts like "If I was designing this I would consider..." on many occasions. With the extraordinary Parallella board we have a unique opportunity to shape it's interfacing and expansion and take it places where its predecessors' could not easily venture. Thus I have written up a short piece with this in mind describing how we could build a sophisticated expansion ecosystem worthy of the Parallela's ground breaking offering. The daughter card post is merely an outline, the start of a conversation around how we can create the best possible expansion system in the opensource hardware market place, so please take a look and use this thread to discuss where we can take this.

Thoughts?

regards
Al
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Re: Daughter card proposal

Postby tnt » Tue Feb 19, 2013 4:19 pm

Interesting idea.

It would be interesting to test the routing needed remap the ports, see if "it works out" even on 2 layer board.

It could also be possible to have an I2C EEPROM connected to the PEC POWER i2c bus to have auto enumeration. We'd need two more GPIO (could be LED0/LED1 abused) connected to a chain of D flip flop (one on each card) whose Q output would be used to select the I2C eeprom address. This way, you can know which card is which and what position it's in the stack, allowing for full auto detection. That would cost less than the connectors most likely :)
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Re: Daughter card proposal

Postby Folknology » Tue Feb 19, 2013 5:18 pm

@tnt your auto enumeration idea is a good one, the possibility had crossed my mind also. I am not sure what the circuit (or runtime use) is behind LED0/1 to make any concrete assumptions as to if these could be easily reused (maybe via a couple of bias transistors perhaps), but if we can find a way of using your clever rippling D-Types on these lines as you suggest it is a distinct possibility, would we also need a reset line, that seems to be missing on the Power connector (PG could be used to generate a local reset pulse)?

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Re: Daughter card proposal

Postby tnt » Tue Feb 19, 2013 8:24 pm

For the autodetect itself, no need for a reset line.

This is what I had in mind :
Image

So to "start", the FPGA just output '0' on the D line and then clocks like 30 times to 'flush' the chain. Then clocks out a '1'. It then reads the eeprom at address '1' (only the first board has this address, the other at at address 0). Then the fpga clocks out a '0', which puts back the first card eeprom to address 0 and puts the second card eeprom on address 1 by itself, and so on ...

Now, do daugther card need a global reset ... no idea. Could definitely be useful, I have to read the serdes chips datasheet more closely to see how to use them.

EDIT: There is even SOT23 EEPROM that could do (beware though, not all sot23 ones have address lines ! but some do). So that would make this circuit a total of 2 SOT23 component. Even if we can't use LED0/1, I think it'd be worth using 2 gpios of PEC FPGA for this. It might be possible to do it with a single one if really needed with a more complex circuitry on the daughterboards.
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Re: Daughter card proposal

Postby gbulmer » Wed Feb 20, 2013 10:07 pm

The proposal for "Parallella Stackable Daughter Boards – Tabs" is very impressive. With that much processing power (which will grow in the future) it is highly desirable to enable very high-bandwidth communication.

However, I wonder if it is more sophisticated than some use-cases require to complete them? I envisage many folks will get the high-bandwidth boards 'ready made' but may have projects which need lower-bandwidth signals too in order to complete them.

After all, Parallella is less than 3x a Raspberry-Pi or Arduino Due. So I think Parallella is within the budget of undergraduate and hobbyist 'embedded' projects. Hence the ability to easily add simple hardware may be an important attraction to a wider user community.

I am assuming there will be a very broad range of interest and capability, with many people having stronger software capabilities and less experience in making hardware. Designing and building a ziport may be more than they feel comfortable doing; for some people it may be an insurmountable obstacle preventing them from applying Parallella.

So, as well as Ziports, also offer something simple, widely available and familiar.

How about SPI? It is simple and fast enough for many simple I/O needs, and much faster than I2C. Using a few of the FPGA PEC's to provide something as 'cheap and cheerful' as SPI may enable folks to get onto the 'Parallella train' and make a more diverse range of 'add-ons' and projects. Most microcontrollers (MCUs) support SPI 'out of the packet', and using an MCU to interface to the 'outside world' may enhance Parallella's flexibility.

For example, a Cortex-M0/3/4 is enough horsepower for simple I/O. Some have as much as 20msps 12-bit ADC, and so could provide interesting data volumes. Cortex microcontrollers start at about $1, so hardware based on those types of devices should be within most projects' student and hackers hardware budgets. Further, the Parallella itself may run the development toolchain for ARM based MCUs.

Even a single SPI would have useful throughput. An Arduino's AVR can handle quite a lot of 'dumb stuff', and it is highly unlikely that it could saturate SPI. Cortex-Mx has more than enough horsepower for a few stepper motors, Brushless DC motors, or closed loop control for DC motors with encoders (using MCU intelligence); some 9+DOF inertial measurement units (IMU) use a Cortex-class processor. Parallella may then be free to handle video, LIDAR, analysis, strategy, etc.

A very simple interface like SPI might enable Parallella to be embedded into a wider variety of projects, while requiring less expertise and time. To get folks started, we might produce a 'skeleton' PCB (e.g. using Eagle), or even one with a low-cost MCU, so folks could easily build the lower-throughput interfaces. For example, someone might add a small LCD display, a few buttons and a LiPo battery charger and monitor, so that Parallella could be embedded in a battery powered device, and used 'in the field'.

The actual use of PEC signals is soft, because of the FPGA, but it would help to recommend a connection strategy to complement the ziport. For example, SPI might start on the left, i.e. the opposite end from ziport, and the signal pin assignments need to be defined.
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Re: Daughter card proposal

Postby tnt » Wed Feb 20, 2013 10:18 pm

I was thinking as well that having a fixed SPI port (there is already I2C) would be a good idea.

It can even be a single port and just use the same 'D-ripple' + NAND gate mechanism to generate the CS# signal so that the same port can be shared by multiple boards.
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Re: Daughter card proposal

Postby theover » Wed Feb 20, 2013 10:48 pm

Come on, you can do a better, more robust digital design than that, which also allows for setup-time correct input, can you ?
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Re: Daughter card proposal

Postby Folknology » Wed Feb 20, 2013 11:27 pm

Thanks for taking the time to read the proposal @gbulmer and providing some great discussion points, here are some of my thoughts regarding your feedback:

gbulmer wrote:The proposal for "Parallella Stackable Daughter Boards – Tabs" is very impressive. With that much processing power (which will grow in the future) it is highly desirable to enable very high-bandwidth communication.

However, I wonder if it is more sophisticated than some use-cases require to complete them? I envisage many folks will get the high-bandwidth boards 'ready made' but may have projects which need lower-bandwidth signals too in order to complete them.

After all, Parallella is less than 3x a Raspberry-Pi or Arduino Due. So I think Parallella is within the budget of undergraduate and hobbyist 'embedded' projects. Hence the ability to easily add simple hardware may be an important attraction to a wider user community.

I am assuming there will be a very broad range of interest and capability, with many people having stronger software capabilities and less experience in making hardware. Designing and building a ziport may be more than they feel comfortable doing; for some people it may be an insurmountable obstacle preventing them from applying Parallella.

So, as well as Ziports, also offer something simple, widely available and familiar.


I think making daughter cards of any sort for the Parallella will represent a challenge for many because of the basic required SMD parts i.e. the Samtec 60 pin connectors (and limited expansion size), there is not easy way to to interface to these other than using sophisticated SMD assembly techniques and components. Given that this raises the bar already, the inclusion of Ziports is only a minor addition on top from the assembly POV IMHO.

One of the things I have started work on is a breakout daughter board (Tab with Ziport back end) that presents 0.1 inch headers to the east, this would provide much simpler IO access and the possibility of hooking up through hole PCBs, peripherals and breadboards. I also intend designing a prototype board including Ziport back end with 0.1 inch holes offering further choices for both entry level and rapid prototyping.

gbulmer wrote:How about SPI? It is simple and fast enough for many simple I/O needs, and much faster than I2C. Using a few of the FPGA PEC's to provide something as 'cheap and cheerful' as SPI may enable folks to get onto the 'Parallella train' and make a more diverse range of 'add-ons' and projects. Most microcontrollers (MCUs) support SPI 'out of the packet', and using an MCU to interface to the 'outside world' may enhance Parallella's flexibility.

For example, a Cortex-M0/3/4 is enough horsepower for simple I/O. Some have as much as 20msps 12-bit ADC, and so could provide interesting data volumes. Cortex microcontrollers start at about $1, so hardware based on those types of devices should be within most projects' student and hackers hardware budgets. Further, the Parallella itself may run the development toolchain for ARM based MCUs.

Even a single SPI would have useful throughput. An Arduino's AVR can handle quite a lot of 'dumb stuff', and it is highly unlikely that it could saturate SPI. Cortex-Mx has more than enough horsepower for a few stepper motors, Brushless DC motors, or closed loop control for DC motors with encoders (using MCU intelligence); some 9+DOF inertial measurement units (IMU) use a Cortex-class processor. Parallella may then be free to handle video, LIDAR, analysis, strategy, etc.

A very simple interface like SPI might enable Parallella to be embedded into a wider variety of projects, while requiring less expertise and time. To get folks started, we might produce a 'skeleton' PCB (e.g. using Eagle), or even one with a low-cost MCU, so folks could easily build the lower-throughput interfaces. For example, someone might add a small LCD display, a few buttons and a LiPo battery charger and monitor, so that Parallella could be embedded in a battery powered device, and used 'in the field'.

The actual use of PEC signals is soft, because of the FPGA, but it would help to recommend a connection strategy to complement the ziport. For example, SPI might start on the left, i.e. the opposite end from ziport, and the signal pin assignments need to be defined.


I agree with you suggestion about the inclusion of SPI, this is a no-brainer for me also, in fact it is top of my Power Connector wish list which I started before reading your comments here! However my preference would be to have SPI on the PEC Power connector rather than the FPGA connector allowing the FPGA_PEC to provide higher bandwidth advantages that you allude in your comments. Also it would be preferable to have the SPI using +3v3 signals rather than +2v5 if at all possible.

regards
Al
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Re: Daughter card proposal

Postby gbulmer » Thu Feb 21, 2013 12:19 am

I think making daughter cards of any sort for the Parallella will represent a challenge for many because of the basic required SMD parts i.e. the Samtec 60 pin connectors (and limited expansion size), there is not easy way to to interface to these other than using sophisticated SMD assembly techniques and components.


I agree SMD devices has to be used, but I think 0.5mm (which I believe is the pitch of BSH-030-01-FDA) is doable using DIY SMD techniques.

I am not expert, but I've made boards using DIY techniques (solder paste syringe and 'toaster oven') for 0.5mm pitch SMD (e.g. http://ourduino.wordpress.com/2011/04/06/orone-cortex-m3-robot-controller-stm32f103/)

In my local schools, 11yo secondary school pupils begin making SMD-based boards, and it is being used increasingly at local universities by undergraduates for projects. There are several PCB suppliers who will make good quality boards for well under $20, hence I still feel the technology is within the reach of many people.

So, I don't think SMD automatically excludes low-cost DIY.

One of the things I have started work on is a breakout daughter board (with Ziport back end) that presents 0.1 inch headers to the east, this would provide much simpler IO access and the possibility of hooking up through hole PCBs, peripherals and breadboards. I also intend designing a prototype board including Ziport back end with 0.1 inch holes offering further choices for both entry level and rapid prototyping.


I think these would be excellent. However, I see them as valuable alternatives, rather than replacements for an SPI-based expansion mechanism.

I agree with you suggestion about the inclusion of SPI, this is a no-brainer for me also, in fact it is top of my Power Connector wish list which I started before reading your comments here! However my preference would be to have SPI on the PEC Power connector rather than the FPGA connector allowing the FPGA_PEC to provide higher bandwidth advantages that you allude in your comments. Also it would be preferable to have the SPI using +3v3 signals rather than +2v5 if at all possible.


3.3V SPI would be better, making a daughterboard design even simpler. Also having it on PEC power may be better and cheaper, as that might mean only one fine-pitch connector has to be attached to a daughterboard.
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Re: Daughter card proposal

Postby Folknology » Thu Feb 21, 2013 10:54 am

gbulmer wrote:
I agree SMD devices has to be used, but I think 0.5mm (which I believe is the pitch of BSH-030-01-FDA) is doable using DIY SMD techniques.

I am not expert, but I've made boards using DIY techniques (solder paste syringe and 'toaster oven') for 0.5mm pitch SMD (e.g. http://ourduino.wordpress.com/2011/04/06/orone-cortex-m3-robot-controller-stm32f103/)

In my local schools, 11yo secondary school pupils begin making SMD-based boards, and it is being used increasingly at local universities by undergraduates for projects. There are several PCB suppliers who will make good quality boards for well under $20, hence I still feel the technology is within the reach of many people.

So, I don't think SMD automatically excludes low-cost DIY.



I don't doubt many folks ability to to be able to find ways and techniques of tackling SMD construction using low cost improvisation its not just ameteurs but professional who also do this on a regular basis in their homes (I have also shown many people how to tackle SMD with low cost tooling) ;-) Although I don't have any of the connector samples handy there design description indicates a DIY challenge similar to QFN like packaging where the pads are primarily under the connector with very little if any of it exposed so they will be a challenge.

What I am more interested about here however is what you think Ziports in particular are adding in terms of construction that make them not "feel comfortable doing" given the hoops already jumped through for the SMD level of construction required for any such boards (Ziport or not). In isolating these obstacles I am interested in how we could overcome them?

gbulmer wrote:
One of the things I have started work on is a breakout daughter board (with Ziport back end) that presents 0.1 inch headers to the east, this would provide much simpler IO access and the possibility of hooking up through hole PCBs, peripherals and breadboards. I also intend designing a prototype board including Ziport back end with 0.1 inch holes offering further choices for both entry level and rapid prototyping.


I think these would be excellent. However, I see them as valuable alternatives, rather than replacements for an SPI-based expansion mechanism.

I agree with you suggestion about the inclusion of SPI, this is a no-brainer for me also, in fact it is top of my Power Connector wish list which I started before reading your comments here! However my preference would be to have SPI on the PEC Power connector rather than the FPGA connector allowing the FPGA_PEC to provide higher bandwidth advantages that you allude in your comments. Also it would be preferable to have the SPI using +3v3 signals rather than +2v5 if at all possible.


3.3V SPI would be better, making a daughterboard design even simpler. Also having it on PEC power may be better and cheaper, as that might mean only one fine-pitch connector has to be attached to a daughterboard.


Reading @trioflex comments on the Power PEC wishlist thread it looks as though we maybe scuppered re adding SPI there, in which case we would have to resort to using some of those valuable high bandwidth FPGA PEC pins which is disappointing. Not only that but any such use would, I believe he is indicating, be at +2v5 rather than +3v3 unless someone more knowledgeable has an alternative, this also makes them much less useful of course.

regards
Al
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