JTAG interface

Sub forum for Parallella daughter cards and accessories

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JTAG interface

Postby ESI » Tue Jun 10, 2014 10:17 pm

The most urgent thing I need, is a JTAG interface.
I have some samples of the samtec connector, so I decided to use one to connect JTAG.
I designed a small pcb, only covering the PEC-Power.
please have a look and tell me if something could be improved. (eagle files attached)

some explanation:
I will solder the pcb by hand (samtec connect probably under microscope) So I enlarge the smd-pad for the samtec connector for better soldering.
The Xilinx connector is not tested in size right now. The resisitors are 0805 and the pads are big enough to solder by hand.
Attachments
ParallellaJTAG.tar.gz
(36.53 KiB) Downloaded 546 times
ESI
 
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Re: JTAG interface

Postby tnt » Tue Jun 10, 2014 10:26 pm

ESI wrote:The most urgent thing I need, is a JTAG interface.


I'm kind of curious why ?

I mean, I've been working for some time with the fpga part of the parallella and I haven't needed the JTAG yet. You can dynamically load a new bitstream from linux, so I'm kind of curious what application you have in mind that needs JTAG so badly ?

Cheers,

Sylvain
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Re: JTAG interface

Postby ESI » Tue Jun 10, 2014 11:00 pm

Hi,
1.
I am having some irregularities with USB as many others do. To look deeper into that matter, I want to look at the EHCI-registers, with JTAG and SDK you can easily do that without disturbing the kernel. I know /dev/mem and mmap would also be an alternative.
2.
I do not trust the FSBL build with Planahead 14.4, so I am going to rebuild the FSBL with 14.7, which I trust more. During my job I also use Zynq, and in 14.7. many things (e.g. wrong PLL settings) have been fixed. Changing the FSBL means flashing the QSPI, means a chance to brick, means I need JTAG to unbrick eventually.
3. I need to change some setting within the FSBL, so same reason, I want the security, that I can unbrick my parallella.

OT: For the USB, I am also planning a Kernel update to the branch master_next of the Xilinx-branch. In another Zynq-based project this fixed eMMC without changing eMMC-driver, so something else, maybe clock, was broken in elder version... just a try.
ESI
 
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Re: JTAG interface

Postby ESI » Wed Jun 11, 2014 11:20 pm

I guess, I need to correct me the latest Planahead files are from 14.7...
ESI
 
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Re: JTAG interface

Postby FHuettig » Fri Jun 13, 2014 3:26 am

ESI wrote:I designed a small pcb, only covering the PEC-Power.


Hi ESI. I've been using the Zebax breakout board, it's not cheap but may be cheaper than spinning your own PCB if you only need one for debug & de-brick. It's definitely cheaper if you value your time!

ESI wrote:I guess, I need to correct me the latest Planahead files are from 14.7...


They are, but be careful because the 14.7 SDK is not compatible with the FSBL & u-boot & kernel that are in our binary distributions. This is a big reason we haven't gone to Vivado yet, it requires many other updates before everything will work together.

Sylvain, another great use for JTAG is ChipScope, if doing work in the PL fabric.

Cheers.
-- Fred -- Hardware Guy --
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Re: JTAG interface

Postby ESI » Fri Jun 20, 2014 11:53 pm

Hi there,
JTAG works now, so no excuses for me not to start debugging, updating etc...
see attached pictures.
My test was:
>xmd
XMD> connect arm hw

then I saw the two taps of zynq...
and was happy for ever after....
Attachments
parallella_w_hs2.jpg
parallella_w_hs2.jpg (22.01 KiB) Viewed 9466 times
parallella_w_jtag.jpg
parallella_w_jtag.jpg (19 KiB) Viewed 9466 times
jtag.jpg
jtag.jpg (10.27 KiB) Viewed 9466 times
ESI
 
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