ARM JTAG

Any technical questions about the Epiphany chip and Parallella HW Platform.

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ARM JTAG

Postby rmorris » Thu Feb 14, 2013 2:55 pm

Will there be access to the ARM JTAG on the parallella board? According to the Zynq-7000 overview at http://www.xilinx.com/support/documentation/zynq-7000.htm there are two JTAG ports available that can be chained together or used separately, the ARM processor JTAG and the FPGA JTAG. I understand from the boot sources thread http://forums.parallella.org/viewtopic.php?f=10&t=164 that the FPGA JTAG will be accessible. Will the ARM JTAG be available too, either chained to the FPGA JTAG or on a separate header? This would be very useful for low-level debugging, reflashing the bootloader etc.
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Re: ARM JTAG

Postby trioflex » Thu Feb 14, 2013 2:57 pm

rmorris wrote:Will there be access to the ARM JTAG on the parallella board? According to the Zynq-7000 overview at http://www.xilinx.com/support/documentation/zynq-7000.htm there are two JTAG ports available that can be chained together or used separately, the ARM processor JTAG and the FPGA JTAG. I understand from the boot sources thread http://forums.parallella.org/viewtopic.php?f=10&t=164 that the FPGA JTAG will be accessible. Will the ARM JTAG be available too, either chained to the FPGA JTAG or on a separate header? This would be very useful for low-level debugging, reflashing the bootloader etc.


PJTAG is NOT available on MIO pins (used by other peripherals!), but it can be routed to PEC_FPGA for ARM Debug

Antti
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Re: ARM JTAG

Postby rmorris » Thu Feb 14, 2013 3:27 pm

trioflex wrote:PJTAG is NOT available on MIO pins (used by other peripherals!), but it can be routed to PEC_FPGA for ARM Debug


Does this mean that under certain circumstances it would not be possible to recover from a bad bootloader flash, i.e. that the Parallella board would be bricked? As I understand it, on the Zync the bootloader is also responsible for loading the bitstream onto the FPGA, so if the bootloader is nonfunctional, it can't route PJTAG to PEC_FPGA, from where one could connect via JTAG. (Sorry, I don't really grok FPGAs...)

Or does it mean that the recovery procedure from a bad bootloader flash would be:
  • Reprogram FPGA via FPGA JTAG to route PJTAG to PEC_FPGA
  • Connect to PJTAG via PEC_FPGA and reflash bootloader
??
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Re: ARM JTAG

Postby trioflex » Thu Feb 14, 2013 4:48 pm

rmorris wrote:
trioflex wrote:PJTAG is NOT available on MIO pins (used by other peripherals!), but it can be routed to PEC_FPGA for ARM Debug


Does this mean that under certain circumstances it would not be possible to recover from a bad bootloader flash, i.e. that the Parallella board would be bricked? As I understand it, on the Zync the bootloader is also responsible for loading the bitstream onto the FPGA, so if the bootloader is nonfunctional, it can't route PJTAG to PEC_FPGA, from where one could connect via JTAG. (Sorry, I don't really grok FPGAs...)

Or does it mean that the recovery procedure from a bad bootloader flash would be:
  • Reprogram FPGA via FPGA JTAG to route PJTAG to PEC_FPGA
  • Connect to PJTAG via PEC_FPGA and reflash bootloader
??


You are right that erasing SPI flash would brick Parallella, but for recovery you need only FPGA hardware JTAG what is dedicated and accessible interface.

ARM debugging is also possible over this JTAG.

But for some software debugging access to PJTAG could be better, that is only possible using EMIO multiplexing to FPGA PL IO Pins. Not needed for most mortals ever.

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Re: ARM JTAG

Postby rmorris » Thu Feb 14, 2013 5:12 pm

trioflex wrote:You are right that erasing SPI flash would brick Parallella, but for recovery you need only FPGA hardware JTAG what is dedicated and accessible interface.

ARM debugging is also possible over this JTAG.

But for some software debugging access to PJTAG could be better, that is only possible using EMIO multiplexing to FPGA PL IO Pins. Not needed for most mortals ever.


One situation where both the ability to reflash the SPI (and recover from bad flashes which leave the bootloader nonfunctional) and access to the ARM JTAG are important is bootloader development.
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Re: ARM JTAG

Postby trioflex » Thu Feb 14, 2013 5:17 pm

rmorris wrote:
trioflex wrote:You are right that erasing SPI flash would brick Parallella, but for recovery you need only FPGA hardware JTAG what is dedicated and accessible interface.

ARM debugging is also possible over this JTAG.

But for some software debugging access to PJTAG could be better, that is only possible using EMIO multiplexing to FPGA PL IO Pins. Not needed for most mortals ever.


One situation where both the ability to reflash the SPI (and recover from bad flashes which leave the bootloader nonfunctional) and access to the ARM JTAG are important is bootloader development.


No, you don't need ARM dedicated PJTAG to be accessible for boot loader development. ARM JTAG is visible as second TAP in main JTAG scan path.

Besides there is really no reason todo much bootloader development on Parallella, just use Zedbaord. Or some other Zynq board-module.
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Re: ARM JTAG

Postby rmorris » Thu Feb 14, 2013 5:25 pm

trioflex wrote:Besides there is really no reason todo much bootloader development on Parallella, just use Zedbaord. Or some other Zynq board-module.


Cost is one reason to choose the Parallella over the Zedboard for bootloader development... :)
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Re: ARM JTAG

Postby trioflex » Thu Feb 14, 2013 5:35 pm

rmorris wrote:
trioflex wrote:Besides there is really no reason todo much bootloader development on Parallella, just use Zedbaord. Or some other Zynq board-module.


Cost is one reason to choose the Parallella over the Zedboard for bootloader development... :)


Parallella as Zynq development platform?

Well, to be honest I did think of that too.. initially but look at the reality, if you need todo Zynq you have to get something that is available.. available NOW

not wait for something that is cheap. Sorry, I do not like waiting. I really was almost to trash 99USD for Parallella, but for me the promise for May 2013 was not good enough, too late..!

As of development for Zynq you can do a lot on virtual platform or Zynq QEMU, costs you exactly 0.00!
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Re: ARM JTAG

Postby ESI » Sat Feb 16, 2013 10:09 am

Hi,
for me, i do not like the idea, that I could brick the board. I would e afraid to go anything near the possibility of bricking.
What I am missing too, is an access to a reset via PEC. I am not a HW engineer, but a SW engineer and actually working on Zynq7020.
What I need to feel safe regarding bricked boards, is the possibility to connect a XILINX plattform cable to a JTAG (via daughter board is ok) of the Zynq, connect it (XMD would be my choice) and reset the whole SOC and then have full access to the Zynq.
My inputs in XMD would be:
> connect arm hw
> rst
The Zynq SOC should be reset now.
Usually in this stage of boot the FPGA is not configured, I think.
If you have this access, anyone could do the unbricking via JTAG.

On the other hand, when you do not have this access, how is the parallella board being bootstrapped after production?
Zynq would be empty, I guess.

br
ESI
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Re: ARM JTAG

Postby trioflex » Sat Feb 16, 2013 1:08 pm

ESI wrote:Hi,
for me, i do not like the idea, that I could brick the board. I would e afraid to go anything near the possibility of bricking.
What I am missing too, is an access to a reset via PEC. I am not a HW engineer, but a SW engineer and actually working on Zynq7020.
What I need to feel safe regarding bricked boards, is the possibility to connect a XILINX plattform cable to a JTAG (via daughter board is ok) of the Zynq, connect it (XMD would be my choice) and reset the whole SOC and then have full access to the Zynq.
My inputs in XMD would be:
> connect arm hw
> rst
The Zynq SOC should be reset now.
Usually in this stage of boot the FPGA is not configured, I think.
If you have this access, anyone could do the unbricking via JTAG.

On the other hand, when you do not have this access, how is the parallella board being bootstrapped after production?
Zynq would be empty, I guess.

br
ESI


I have been saying it several times already, if you have JTAG cable connected to Parallella you can unbrick Parallella if that is should be ever needed. There is no need to have access to RST pin.

Zynq has several types of resets it is also possible to reset PS without reconfiguring PL.

Of course it would be nice to actually have RST pin the PEC_power connector, this would allow full compatibility with Xilinx SDK tooks...

If you are able to get hands on onto OLD revision of ZEDboard schematics you can see that FTDI chip is connected to the JTAG pins, and also RST pin. In the current schematic release this page has been removed. So much much about open source - zedboard was initially advertised as open source project but now part of the open has gone CLOSED.
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