The pinout package document you referenced, refers to the following for the XADC document for further pinout description.
My reading of this (admittedly a single cursory reading) is that there are some dedicated package pins in bank zero with a _0 suffix on the names (Ref, p 13), and External Analog Inputs that are "allocated evenly over banks 15 and 35", with a caveat to consult yet another document to be sure. I did find your "Bank 35 contains the XADC auxiliary inputs" quote so maybe Bank 15 is used on the 7000 series FPGA parts but not the SoC parts.
But in any case the dedicated pins listed in UG865 Table 1-2 (p6), are available without any internal conflict. That is:
VP_0 (K9)
VN_0 (L10)
VREFP_0 (L9)
VREFN_0 (K10)
VCCADC_0 (J9)
GNDADC_0 (J10)
The pinouts are from
assuming you're using the CLG400 package.
How do you feel about putting VP_0 and VN_0 on a header and decoupling the others appropriately? It's going to be a PITA to route