rm: cannot remove 'system_wrapper.bit.bin': No such file or directory rm: cannot remove 'bit2bin.bin': No such file or directory ****** Vivado v2017.1 (64-bit) **** SW Build 1846317 on Fri Apr 14 18:54:47 MDT 2017 **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source package.tcl # source ./ip_params.tcl ## set design axi_accelerator ## set projdir ./ ## set root "../.." ## set partname "xc7z010clg400-1" ## set hdl_files [list \ ## $root/accelerator/hdl \ ## $root/common/hdl/ \ ## $root/emesh/hdl \ ## $root/emmu/hdl \ ## $root/axi/hdl \ ## $root/emailbox/hdl \ ## $root/edma/hdl \ ## $root/elink/hdl \ ## ] ## set ip_files [] ## set constraints_files [] # source ../../common/fpga/create_ip.tcl ## create_project -force $design $projdir -part $partname ## set_property target_language Verilog [current_project] ## set_property source_mgmt_mode None [current_project] ## if {[string equal [get_filesets -quiet sources_1] ""]} { ## create_fileset -srcset sources_1 ## } ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files ## set_property top $design [get_filesets sources_1] ## if {[string equal [get_filesets -quiet constraints_1] ""]} { ## create_fileset -constrset constraints_1 ## } ## if {[llength $constraints_files] != 0} { ## add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files ## } ## if {[llength $ip_files] != 0} { ## ## #Add to fileset ## add_files -norecurse -fileset [get_filesets sources_1] $ip_files ## ## #Set mode for IP ## foreach file $ip_files { ## #TODO: is this needed? ## set file_obj [get_files -of_objects [get_filesets sources_1] $file] ## set_property "synth_checkpoint_mode" "Singular" $file_obj ## } ## #RERUN/UPGRADE IP ## upgrade_ip [get_ips] ## } ## ipx::package_project -import_files -force -root_dir $projdir WARNING: [Ipptcl 7-1467] The compile order has been set manually. This prevents the packager from updating it if necessary. If errors related to compile order occur, try enabling automatic reordering, or calling package_project with the -force_update_compile_order option WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'. CRITICAL WARNING: [HDL 9-806] Syntax error near "|". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/oh_mux.v:33] CRITICAL WARNING: [HDL 9-806] Syntax error near "&". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/oh_mux.v:33] CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/oh_mux.v:33] CRITICAL WARNING: [HDL 9-870] Macro is not defined. [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:102] CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:102] CRITICAL WARNING: [HDL 9-870] Macro is not defined. [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:103] CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:126] CRITICAL WARNING: [HDL 9-870] Macro is not defined. [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:131] CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:131] CRITICAL WARNING: [HDL 9-870] Macro is not defined. [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:132] CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:132] CRITICAL WARNING: [HDL 9-806] Syntax error near "|". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/oh_mux.v:33] CRITICAL WARNING: [HDL 9-806] Syntax error near "&". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/oh_mux.v:33] CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/oh_mux.v:33] CRITICAL WARNING: [HDL 9-870] Macro is not defined. [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:102] CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:102] CRITICAL WARNING: [HDL 9-870] Macro is not defined. [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:103] CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:126] CRITICAL WARNING: [HDL 9-870] Macro is not defined. [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:131] CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:131] CRITICAL WARNING: [HDL 9-870] Macro is not defined. [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:132] CRITICAL WARNING: [HDL 9-806] Syntax error near ")". [/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/src/emailbox.v:132] INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/accelerator_regmap.v" from the top-level HDL file. INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/emailbox_regmap.v" from the top-level HDL file. INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/elink_regmap.v" from the top-level HDL file. INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/elink_constants.v" from the top-level HDL file. INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.1/data/ip'. INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 's_axi_aresetn' as interface 's_axi_aresetn'. INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'm_axi_aresetn' as interface 'm_axi_aresetn'. INFO: [IP_Flow 19-4728] Bus Interface 'm_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4753] Inferred signal 'interrupt' from port 'irq' as interface 'irq'. INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'. INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'sys_clk' as interface 'sys_clk'. INFO: [IP_Flow 19-818] Not transferring value dependency attribute "((2 * spirit:decode(id('MODELPARAM_VALUE.AW'))) + 40)" into user parameter "PW". ## ipx::remove_memory_map {s_axi} [ipx::current_core] ## ipx::add_memory_map {s_axi} [ipx::current_core] ## ipx::associate_bus_interfaces -busif s_axi -clock sys_clk [ipx::current_core] INFO: [IP_Flow 19-4728] Bus Interface 'sys_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'. ## ipx::associate_bus_interfaces -busif m_axi -clock sys_clk [ipx::current_core] WARNING: command 'get_bus_interface' will be removed in the 2015.3 release, use 'get_bus_interfaces' instead ## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interface s_axi [ipx::current_core]] WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead ## ipx::add_address_block {axi_lite} [ipx::get_memory_map s_axi [ipx::current_core]] WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead WARNING: command 'get_address_block' will be removed in the 2015.3 release, use 'get_address_blocks' instead ## set_property range {65536} [ipx::get_address_block axi_lite \ ## [ipx::get_memory_map s_axi [ipx::current_core]]] ## set_property vendor {www.parallella.org} [ipx::current_core] ## set_property library {user} [ipx::current_core] ## set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core] ## set_property vendor_display_name {ADAPTEVA} [ipx::current_core] ## set_property company_url {www.parallella.org} [ipx::current_core] ## set_property supported_families { \ ## {virtex7} {Production} \ ## {qvirtex7} {Production} \ ## {kintex7} {Production} \ ## {kintex7l} {Production} \ ## {qkintex7} {Production} \ ## {qkintex7l} {Production} \ ## {artix7} {Production} \ ## {artix7l} {Production} \ ## {aartix7} {Production} \ ## {qartix7} {Production} \ ## {zynq} {Production} \ ## {qzynq} {Production} \ ## {azynq} {Production} \ ## } [ipx::current_core] WARNING: [IP_Flow 19-4623] Unrecognized family virtex7. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qvirtex7. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7l. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qartix7. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qzynq. Please verify spelling and reissue command to set the supported files. ## ipx::archive_core [concat $design.zip] [ipx::current_core] ## exit INFO: [Common 17-206] Exiting Vivado at Fri Jun 9 16:54:33 2017... ****** Vivado v2017.1 (64-bit) **** SW Build 1846317 on Fri Apr 14 18:54:47 MDT 2017 **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source run.tcl # source ./run_params.tcl ## set design system ## set projdir ./ ## set partname "xc7z010clg400-1" ## set ip_repos [list "."] ## set hdl_files [] ## set constraints_files [] # source ../../common/fpga/system_init.tcl ## create_project -force $design $projdir -part $partname ## set_property target_language Verilog [current_project] ## set report_dir $projdir/reports ## set results_dir $projdir/results ## if ![file exists $report_dir] {file mkdir $report_dir} ## if ![file exists $results_dir] {file mkdir $results_dir} ## set other_repos [get_property ip_repo_paths [current_project]] ## set_property ip_repo_paths "$ip_repos $other_repos" [current_project] ## update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.1/data/ip'. ## create_bd_design "system" Wrote : ## source $projdir/system_bd.tcl ### namespace eval _tcl { ### proc get_script_folder {} { ### set script_path [file normalize [info script]] ### set script_folder [file dirname $script_path] ### return $script_folder ### } ### } ### variable script_folder ### set script_folder [_tcl::get_script_folder] ### set scripts_vivado_version 2017.1 ### set current_vivado_version [version -short] ### if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { ### puts "" ### catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} ### ### return 1 ### } ### set list_projs [get_projects -quiet] ### if { $list_projs eq "" } { ### create_project project_1 myproj -part xc7z020clg400-1 ### } ### set design_name system ### set errMsg "" ### set nRet 0 ### set cur_design [current_bd_design -quiet] ### set list_cells [get_bd_cells -quiet] ### if { ${design_name} eq "" } { ### # USE CASES: ### # 1) Design_name not set ### ### set errMsg "Please set the variable to a non-empty value." ### set nRet 1 ### ### } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { ### # USE CASES: ### # 2): Current design opened AND is empty AND names same. ### # 3): Current design opened AND is empty AND names diff; design_name NOT in project. ### # 4): Current design opened AND is empty AND names diff; design_name exists in project. ### ### if { $cur_design ne $design_name } { ### common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." ### set design_name [get_property NAME $cur_design] ### } ### common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." ### ### } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { ### # USE CASES: ### # 5) Current design opened AND has components AND same names. ### ### set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." ### set nRet 1 ### } elseif { [get_files -quiet ${design_name}.bd] ne "" } { ### # USE CASES: ### # 6) Current opened design, has components, but diff names, design_name exists in project. ### # 7) No opened design, design_name exists in project. ### ### set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." ### set nRet 2 ### ### } else { ### # USE CASES: ### # 8) No opened design, design_name not in project. ### # 9) Current opened design, has components, but diff names, design_name not in project. ### ### common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." ### ### create_bd_design $design_name ### ### common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." ### current_bd_design $design_name ### ### } INFO: [BD_TCL-2] Constructing design in IPI design ... ### common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." INFO: [BD_TCL-5] Currently the variable is equal to "system". ### if { $nRet != 0 } { ### catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} ### return $nRet ### } ### proc create_root_design { parentCell } { ### ### variable script_folder ### ### if { $parentCell eq "" } { ### set parentCell [get_bd_cells /] ### } ### ### # Get object for parentCell ### set parentObj [get_bd_cells $parentCell] ### if { $parentObj == "" } { ### catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} ### return ### } ### ### # Make sure parentObj is hier blk ### set parentType [get_property TYPE $parentObj] ### if { $parentType ne "hier" } { ### catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} ### return ### } ### ### # Save current instance; Restore later ### set oldCurInst [current_bd_instance .] ### ### # Set parent object as current ### current_bd_instance $parentObj ### ### ### # Create interface ports ### ### # Create ports ### ### # Create instance: axi_accelerator_0, and set properties ### set axi_accelerator_0 [ create_bd_cell -type ip -vlnv www.parallella.org:user:axi_accelerator:1.0 axi_accelerator_0 ] ### ### set_property -dict [ list \ ### CONFIG.SUPPORTS_NARROW_BURST {1} \ ### CONFIG.NUM_READ_OUTSTANDING {2} \ ### CONFIG.NUM_WRITE_OUTSTANDING {2} \ ### CONFIG.MAX_BURST_LENGTH {256} \ ### ] [get_bd_intf_pins /axi_accelerator_0/m_axi] ### ### set_property -dict [ list \ ### CONFIG.NUM_READ_OUTSTANDING {2} \ ### CONFIG.NUM_WRITE_OUTSTANDING {2} \ ### ] [get_bd_intf_pins /axi_accelerator_0/s_axi] ### ### # Create instance: proc_sys_reset_0, and set properties ### set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] ### ### # Create instance: processing_system7_0, and set properties ### set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] ### set_property -dict [ list \ ### CONFIG.PCW_CORE0_FIQ_INTR {0} \ ### CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ ### CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ ### CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ ### CONFIG.PCW_EN_CLK3_PORT {1} \ ### CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ ### CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {100} \ ### CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ ### CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ ### CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ ### CONFIG.PCW_I2C0_I2C0_IO {EMIO} \ ### CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_I2C0_RESET_ENABLE {0} \ ### CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ ### CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ ### CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} \ ### CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ ### CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_UART1_UART1_IO {MIO 8 .. 9} \ ### CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.434} \ ### CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.398} \ ### CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.410} \ ### CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.455} \ ### CONFIG.PCW_UIPARAM_DDR_CL {9} \ ### CONFIG.PCW_UIPARAM_DDR_CWL {9} \ ### CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {8192 MBits} \ ### CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.315} \ ### CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.391} \ ### CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.374} \ ### CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.271} \ ### CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {32 Bits} \ ### CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {400.00} \ ### CONFIG.PCW_UIPARAM_DDR_PARTNO {Custom} \ ### CONFIG.PCW_UIPARAM_DDR_T_FAW {50} \ ### CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {40} \ ### CONFIG.PCW_UIPARAM_DDR_T_RC {60} \ ### CONFIG.PCW_UIPARAM_DDR_T_RCD {9} \ ### CONFIG.PCW_UIPARAM_DDR_T_RP {9} \ ### CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} \ ### CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_USB0_RESET_ENABLE {0} \ ### CONFIG.PCW_USB1_PERIPHERAL_ENABLE {1} \ ### CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ ### CONFIG.PCW_USE_M_AXI_GP1 {1} \ ### CONFIG.PCW_USE_S_AXI_HP1 {1} \ ### ] $processing_system7_0 ### ### # Create instance: processing_system7_0_axi_periph, and set properties ### set processing_system7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 processing_system7_0_axi_periph ] ### set_property -dict [ list \ ### CONFIG.NUM_MI {1} \ ### ] $processing_system7_0_axi_periph ### ### # Create interface connections ### connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP1 [get_bd_intf_pins processing_system7_0/M_AXI_GP1] [get_bd_intf_pins processing_system7_0_axi_periph/S00_AXI] ### connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_accelerator_0/s_axi] [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI] ### ### # Create port connections ### connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins processing_system7_0_axi_periph/ARESETN] ### connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_accelerator_0/m_axi_aresetn] [get_bd_pins axi_accelerator_0/s_axi_aresetn] [get_bd_pins axi_accelerator_0/sys_nreset] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] ### connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_accelerator_0/sys_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] ### connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] ### ### # Create address segments ### create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_accelerator_0/s_axi/axi_lite] SEG_axi_accelerator_0_axi_lite ### ### ### # Restore current instance ### current_bd_instance $oldCurInst ### ### save_bd_design ### } ### create_root_design "" WARNING: [BD 41-1753] The name 'processing_system7_0_axi_periph' you have specified is long. The Windows OS has path length limitations. It is recommended you use shorter names(less than 25 characters) to reduce the likelihood of issues when/if running on windows OS. WARNING: [BD 41-1731] Type mismatch between connected pins: /axi_accelerator_0/sys_nreset(undef) and /proc_sys_reset_0/peripheral_aresetn(rst) Wrote : ## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top Wrote : Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v ## if {[string equal [get_filesets -quiet sources_1] ""]} { ## create_fileset -srcset sources_1 ## } ## set top_wrapper $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v ## add_files -norecurse -fileset [get_filesets sources_1] $top_wrapper ## if {[llength $hdl_files] != 0} { ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files ## } ## if {[string equal [get_filesets -quiet constrs_1] ""]} { ## create_fileset -constrset constrs_1 ## } ## if {[llength $constraints_files] != 0} { ## add_files -norecurse -fileset [get_filesets constrs_1] $constraints_files ## } # source ../../common/fpga/system_build.tcl ## validate_bd_design INFO: [BD 5-320] Validate design is not run, since the design is already validated. ## write_bd_tcl -force ./system_bd.tcl INFO: [BD 5-148] Tcl file written out . ## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v ## remove_files -fileset sources_1 $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v ## add_files -fileset sources_1 -norecurse $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v ## launch_runs synth_1 INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run. Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v Verilog Output written to : /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_accelerator_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.srcs/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0_axi_periph/s00_couplers/auto_pc . Exporting to file /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.srcs/sources_1/bd/system/hw_handoff/system.hwh Generated Block Design Tcl file /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl Generated Hardware Definition File /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.hwdef [Fri Jun 9 16:55:05 2017] Launched system_axi_accelerator_0_0_synth_1, system_auto_pc_0_synth_1, system_processing_system7_0_0_synth_1, system_proc_sys_reset_0_0_synth_1... Run output will be captured here: system_axi_accelerator_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/system_axi_accelerator_0_0_synth_1/runme.log system_auto_pc_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/system_auto_pc_0_synth_1/runme.log system_processing_system7_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/system_processing_system7_0_0_synth_1/runme.log system_proc_sys_reset_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/system_proc_sys_reset_0_0_synth_1/runme.log [Fri Jun 9 16:55:05 2017] Launched synth_1... Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/synth_1/runme.log launch_runs: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1435.328 ; gain = 129.727 ; free physical = 142 ; free virtual = 3986 ## wait_on_run synth_1 [Fri Jun 9 16:55:05 2017] Waiting for synth_1 to finish... [Fri Jun 9 16:56:37 2017] synth_1 finished wait_on_run: Time (s): cpu = 00:01:29 ; elapsed = 00:01:33 . Memory (MB): peak = 1435.328 ; gain = 0.000 ; free physical = 829 ; free virtual = 3989 ## launch_runs impl_1 [Fri Jun 9 16:56:39 2017] Launched system_axi_accelerator_0_0_synth_1, system_proc_sys_reset_0_0_synth_1, synth_1... Run output will be captured here: system_axi_accelerator_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/system_axi_accelerator_0_0_synth_1/runme.log system_proc_sys_reset_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/system_proc_sys_reset_0_0_synth_1/runme.log synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/synth_1/runme.log [Fri Jun 9 16:56:39 2017] Launched impl_1... Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/impl_1/runme.log ## wait_on_run impl_1 [Fri Jun 9 16:56:39 2017] Waiting for impl_1 to finish... [Fri Jun 9 16:56:52 2017] impl_1 finished wait_on_run: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1435.328 ; gain = 0.000 ; free physical = 816 ; free virtual = 3986 ## launch_runs impl_1 -to_step write_bitstream [Fri Jun 9 16:56:53 2017] Launched system_axi_accelerator_0_0_synth_1, system_proc_sys_reset_0_0_synth_1, synth_1... Run output will be captured here: system_axi_accelerator_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/system_axi_accelerator_0_0_synth_1/runme.log system_proc_sys_reset_0_0_synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/system_proc_sys_reset_0_0_synth_1/runme.log synth_1: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/synth_1/runme.log [Fri Jun 9 16:56:53 2017] Launched impl_1... Run output will be captured here: /home/promach/Documents/Grive/Personal/Digital/Parallella/parallella-riscv/parallella/oh/accelerator/fpga/system.runs/impl_1/runme.log ## wait_on_run impl_1 [Fri Jun 9 16:56:53 2017] Waiting for impl_1 to finish... [Fri Jun 9 16:57:07 2017] impl_1 finished wait_on_run: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1435.328 ; gain = 0.000 ; free physical = 794 ; free virtual = 3985 INFO: [Common 17-206] Exiting Vivado at Fri Jun 9 16:57:07 2017... [ERROR] : Can't read BIT file - ./system.runs/impl_1/system_wrapper.bit cp: cannot stat 'system_wrapper.bit.bin': No such file or directory